Motorola MPC860 PowerQUICC, User Manual

Page: 311 / 1106

MOTOROLA Chapter 12. Reset 12-3
Part III. Configuration
HRESET and SRESET signals high. See Section 12.3.1, ÒHard Reset,Ó for more
information.
The causes of internal hard reset are as follows:
¥ PLL loss of lock
¥ Software watchdog reset
¥ Checkstop reset
¥ Debug port hard reset
The following sections describe the events that can initiate an internal assertion of the
HRESET and SRESET signals.
12.1.3.1 PLL Loss of Lock
If the PLL experiences a loss of lock erroneous external bus operation may occur.
Erroneous operation can also occur if devices with a PLL use the core CLKOUT signal as
a driver. If PLPRCR[LOLRE] = 1 and a PLL loss-of-lock event occurs, an internal hard
reset sequence is generated.
12.1.3.2 Software Watchdog Reset
When SRS[SWRS] = 1 and the core watchdog counter decrements to zero, a software
watchdog reset is asserted generating an internal hard reset sequence.
12.1.3.3 Checkstop Reset
If the core enters a checkstop state and PLPRCR[CSR] = 1, the checkstop reset is asserted
generating an internal hard reset sequence.
12.1.4 Debug Port Hard or Soft Reset
When the development port receives a hard or soft reset request from a development tool,
an internal hard or soft reset sequence is generated. The development tool must reconÞgure
the debug port following a reset event. See Section 37.3.2.1.2, ÒDevelopment Serial Data
In (DSDI).Ó
12.1.5 JTAG Reset
When the JTAG logic asserts the JTAG reset signal, an internal soft reset sequence will be
generated.