Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-9
Part V. The Communications Processor Module
Table 26-6 describes reception errors.
26.13 SCC Asynchronous HDLC Registers
The following sections describe the SCC registers when in asynchronous HDLC mode.
26.13.1 Asynchronous HDLC Event Register (SCCE)/Asynchronous
HDLC Mask Register (SCCM)
The SCC event register (SCCE) is used as the asynchronous HDLC event register to
generate interrupts and report events recognized by the asynchronous HDLC channel.
When an event is recognized, the asynchronous HDLC controller sets the corresponding
SCCE bit. Interrupts can be masked by clearing the appropriate bit in the asynchronous
HDLC mask register (SCCM). SCCE bits, shown in Figure 26-4, are cleared by writing
onesÑwriting zeros has no effect. Unmasked SCCE bits must be cleared before the CPM
clears the internal interrupt request.
Table 26-6. Receive Errors
Error Description
Overrun SCC1 has 32-byte Rx FIFOs; other SCCs have 16-byte Rx FIFOs. Overrun occurs when the CP
cannot keep up with the data rate or the SDMA channel cannot write the received data to memory. The
previous data byte and frame status are lost. The controller closes the buffer and sets RxBD[OV] and
SCCE[RXF]. The receiver then looks for the next frame.
CD Lost
during Frame
Reception The channel stops receiving frames, closes the buffer, and sets SCCE[RXF] and RxBD[CD]. This error
has highest priority. The rest of the frame is lost and other errors are not checked in that frame. The
receiver then searches for the next frame once CD is reasserted.
Abort
Sequence When an abort sequence (0x7D, 0x7E for PPP; 0x7D, 0xC1 for IrLAP) is detected, the channel closes
the buffer by setting SCCE[RXF] and RxBD[AB]. CRC error status is not checked on aborted frames.
If no frame is being received, the next BD is opened and then closed with RxBD[AB] set.
CRC The channel writes the received cyclic redundancy check to the buffer, closes the buffer, and sets
SCCE[RXF] and RxBD[CR]. After receiving this error, the receiver prepares to receive the next frame.
Break
Sequence
Received The receiver detected the Þrst character in a break sequence. The channel closes the buffer and sets
SCCE[RXF] and RxBD[BRK]. CRC error status is not checked. SCCE[BRKS] is set when the Þrst
break of a sequence is found; SCCE[BRKE] is set when an idle bit is received after a break sequence.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ GLR GLT Ñ IDL Ñ BRKE BRKS TXE RXF BSY TXB RXB
Reset 0
R/W R/W
Addr 0xA10 (SCCE1)/0xA14 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2)
0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)
Figure 26-4. Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC
Mask Register (SCCM)