Motorola MPC860 PowerQUICC, User Manual

Page: 561 / 1106

MOTOROLA Chapter 19. Communications Processor 19-13
Part V. The Communications Processor Module
timer. (Using
SET TIMER
properly synchronizes the timer table modiÞcations to the
execution of the CP.)
19.7.2 The
SET TIMER
Command
Issued to the CP command register (CPCR), the
SET TIMER
command is used to enable,
disable, and conÞgure the 16 timers in the RISC timer table. Set up the TM_CMD value in
the RISC timer table parameter RAM before writing 0x0851 to the CPCR.
19.7.3 RISC Timer Table Parameter RAM and Timer Table Entries
Two areas of dual-port RAM are used for the RISC timer tableÑRISC timer table
parameter RAM and the RISC timer table entries; see Figure 19-6.
Figure 19-6. RISC Timer Table RAM Usage
The RISC timer table parameter RAM holds the general timer parameters. Table 19-9
shows its memory map.
Table 19-9. RISC Timer Table Parameter RAM Memory Map
Offset
1
Name Width Description
0x00 TM_BASE Hword RISC timer table base address. The actual timers are a small block of memory in the
dual-port RAM. TM_BASE is the offset from the beginning of the dual-port RAM where
that block of memory resides. Four bytes must be reserved at the TM_BASE for each
timer used, (64 bytes if all 16 timers are used). If fewer than 16 timers are used, timers
should be allocated in ascending order to save space. For example, 8 bytes are
required if two timers are needed and RISC timers 0 and 1 are enabled.
TM_BASE should be word-aligned.
0x02 TM_PTR Hword RISC timer table pointer. Only the CP uses this register to point to the next timer
accessed in the timer table. Do not modify this register.
TM_BASE
16 RISC
Timer Table
Entries
(Up to 64 Bytes)
RISC
Timer Table
Parameter RAM
DPRA 0x1DB0
Timer Table Base Pointer