Motorola MPC860 PowerQUICC, User Manual, Page: 585 / 1106

MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-19
Part V. The Communications Processor Module
20.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode)
DCMR contains the channelÕs function code and byte-order convention, previously held in
function code registers. DCMR also holds the channel start bit (enable) and burst transfer
information. Figure 20-13 shows the DCMR format.
Table 20-10 describes the DCMR bit settings for IDMA1 in single-buffer mode.
20.3.9.2 IDMA1 Status Register (IDSR1) (Single-Buffer Mode)
IDSR1 in single-buffer mode behaves the same way as deÞned in Section 20.3.3.2, ÒIDMA
Status Registers (IDSR1 and IDSR2).Ó The only relevant event bit, however, is DONE,
which is set when the byte count in BCR reaches zero. Figure 20-14 shows the register
format.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field 1 Ñ BO AT[1Ð3] STR Ñ BPR
Reset 0000_0000_0000_0000
R/W R/W
Addr IDMA1 Base + 0x08
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ
Reset 0000_0000_0000_0000
R/W R/W
Addr IDMA1 Base + 0x0A
Figure 20-13. IDMA Channel Mode Register (DCMR) (Single-Buffer Mode)
Table 20-10. DCMR Field Descriptions (Single-Buffer Mode)
Bits Name Description
0 Ñ Must be set.
1Ð2 Ñ Reserved. Should be cleared.
3Ð4 BO See corresponding description in Table 20-8 above.
5Ð7 AT[1Ð3] See corresponding description in Table 20-8 above.
8 STR Start. Enables the IDMA channel. Cleared automatically upon completion of the transfer request.
0 Disable IDMA channel.
1 Enable IDMA channel. Set STR after programming BAPR and BCR.
9
Ð
13 Ñ Reserved. Should be cleared.
14Ð15 BPR Bursts per request. Determines how many bursts will be initiated for each request.
00 One burst per request (16 bytes).
01 Two bursts per request (32 bytes).
10 Reserved
11 Four bursts per request (64 bytes).
16
Ð
31 Ñ Reserved. Should be cleared.