Motorola MPC860 PowerQUICC, User Manual

Page: 433 / 1106

MOTOROLA Chapter 16. Memory Controller 16-7
Part IV. Hardware Interface
16.3.1 Address Space Programming
Each bank has an option register (ORx) and a base register (BRx), which contains a V bit
that indicates that the information for the chip-select is valid.
Each base register deÞnes the starting address of its memory bank and each option register
deÞnes the attributes for its memory bank. Option registers also deÞne the initial address
multiplexing for a memory cycle controlled by a UPM. Each time an internal or external
bus cycle access is requested, the address and its corresponding address type are compared
to each bank. If one bank matches, its attributes deÞned in BRx and ORx are used to control
the memory access. If multiple matches occur, the lowest numbered matched bank handles
the access.
16.3.2 Register Programming Order
For UPM-controlled chip selects, UPM registers should be programmed before ORx and
BRx. For all chip selects, ORx should be programmed before BRx except when
programming the boot chip select (CS0) after hardware reset, in which case, BR0 should
be programmed before OR0.
16.3.3 Memory Bank Write Protection
Attempting to write to an address range marked restricted in BRx[WP] causes a
write-protect violation for which MSTAT[WPER] is set.
16.3.4 Address Type Protection
BRx[AT] and ORx[ATM] can be used to implement address-type protection in a manner
similar to the address space programming. Note that when external masters access memory
controller-managed slaves on the bus, the internal AT[0Ð2] signals to the memory controller
are forced to 0b100.
16.3.5 8-, 16-, and 32Bit Port Size ConÞguration
The port size is speciÞed by BRx[PS].Eight-bit ports must be connected to D[0Ð7], 16-bit
ports must be connected to D[0Ð15]. For ports smaller than 32-bits, dynamic bus sizing is
performed for all internal masters, such that only external bus accesses result, such as those
deÞned in Figure 16-2.
Table 16-2. Access Granularities for Predefined Port Sizes
PredeÞned
Port Size
Bytes Half Words
Words (on Word
Boundaries)
Odd Even Odd Even
8-bit
Ö Ö
Ñ Ñ Ñ
16-bit
Ö Ö
Ñ
Ö
(on D[0Ð15]) Ñ
32-bit
Ö Ö Ö Ö Ö