Motorola MPC860 PowerQUICC, User Manual

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11-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part III. Configuration
Table 11-15 describes the DEC register.
11.9 The PowerPC Timebase
The PowerPC timebase is a 64-bit free-running binary counter. For the MPC860, the
timebase is clocked by TMBCLK. The timebase period is as follows:
The timebase is unaffected by RESETH and RESETS and should be initialized by software.
Note, however, that it is disabled and reset by PORESET. The entire timebase cannot be
accessed with a single instruction; mttb and mftb access the lower half of the timebase and
mttbu and mftbu access the upper half. A maskable interrupt is generated when the
timebase count reaches a value programmed in one of the reference registers, TBREFA and
TBREFB; two status bits indicate which one caused the interrupt.
11.9.1 Timebase Register (TBU and TBL)
The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is
implemented in two parts, time base upper and time base lower (TBU and TBL). There is
no automatic initialization of TB, therefore, system software must perform this
initialization. The contents of TB can be written by mtspr and read by mftb or mftbu
instruction. Figure 11-19 shows TBU. Note that the TBU and TBL are keyed registers.
They must be unlocked in TBK before they can be written.
Bit 0 1 2 3 4 5 6 7 8 9 É 30 31
Field DEC
Reset Ñ
R/W R/W
SPR 22
Figure 11-18. Decrementer Register (DEC)
Table 11-15. DEC Field Descriptions
Bits Name Description
0Ð31 DEC Decrementer. These bits are used by a down counter to cause decrementer interrupts. Reading DEC
always returns the current count value from the down counter.
Bit 0 1 2 3 4 5 6 7 8 9 É 30 31
Field TBU
Reset Ñ
R/W R/W
SPR 269 (Read)/285 (Write)
Figure 11-19. Timebase Upper Register (TBU)
T
TB
264
F
tmbclk
------------------------ =