16-32
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part IV. Hardware Interface
External memory access requests are single-beat and burst reads and writes. A single-beat
transfer transfers one operand consisting of a single byte, half word, or word. A burst
transfer transfers four words. A single-beat cycle starts with one transfer start and ends with
one transfer acknowledge. For 32-bit accesses, the burst cycle starts with one transfer start
but ends after four transfer acknowledges. A 16-bit bus requires are 8 transfer
acknowledges; an 8-bit bus requires 16.
16.6.1.2 UPM Periodic Timer Requests
Each UPM contains a periodic timer that can be programmed to generate periodic service
requests of a particular pattern in the RAM array. Figure 16-33 shows the hardware
associated with memory periodic timer request generation. In general, the periodic timer is
used for refresh cycle operation. MxMR[PTx] deÞnes the period for the timers associated
with UPMx. If MxMR[PTxE] is set, the periodic timer of UPMx requests a transaction
when the timer period expires.
Figure 16-33. Memory Periodic Timer Request Block Diagram
16.6.1.3 Software RequestsÑMCR
RUN
Command
Software can start a request to the UPM by issuing a
RUN
command to the MCR. Some
memory devices have their own signal handshaking protocol to put them into special
modes, such as self-refresh mode. Other memory devices must be issued special commands
on their control signals, such as for SDRAM initialization.
For these special cycles, the user creates a special RAM pattern that can be stored in any
unused areas in the UPM RAM. Then the MCR
RUN
command is used to run the cycle. The
UPM runs the pattern beginning at the speciÞed RAM location until it encounters a RAM
word with its LAST bit set.
16.6.1.4 Exception Requests
When the MPC860 under UPM control initiates an access to a memory device, the external
device may assert TEA, SRESET, or HRESET. The UPM provides a mechanism by which
memory control signals can meet the timing requirements of the device without losing data.
The mechanism is the exception pattern which deÞnes how the UPM deasserts its signals
in a controlled manner.
Memory
Periodic
Timer
Periodic
Timer A
(PTA)
Periodic
Timer B
(PTB)
BRG
Prescaler and
(In SCCR)
Prescaler
(In MPTPR)
System Clock
UPMA Periodic
Timer Request
UPMB Periodic
Timer Request
External Bus
Clock
Divider
Summary of Contents for MPC860 PowerQUICC
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Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
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Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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Page 632: ...21 44 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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