Motorola MPC860 PowerQUICC, User Manual, Page: 401 / 1106

MOTOROLA Chapter 15. Clocks and Power Control 15-7
Part IV. Hardware Interface
be maintained steadily throughout PORESET assertion. The MF Þeld is set as shown in
Table 15-1. After PORESET is deasserted, the MODCK[1-2] values are internally latched,
and the signals applied to MODCK[1-2] can then be changed.
Note that under no condition should the voltage on MODCK1 and MODCK2 exceed the
power supply voltage VDDH applied to the part.
At power-on reset, before the PLL achieves lock, no internal or external clocks are
generated by the MPC860 , which may cause higher than normal static current during the
short period of stabilization.
15.2.2.2 SPLL Output Characteristics and Stability
The minimum frequency at which the SPLL is guaranteed to operate is 15 MHz; therefore,
the MPC860 must be conÞgured so that at all times (both after initial system reset and at
the Þnal operating frequency) the minimum frequency of CLKOUT is 15 MHz. The
maximum frequency at which the SPLL is guaranteed to operate is the maximum rated
frequency of the part (for example, 50 MHz for a 50-MHz part).
The multiplication factor is the most important parameter in deÞning the SPLL stability.
There are three factors related to the multiplication factor that deÞne SPLL stability:
¥ Phase skewÑThe time difference between the falling edges of the EXTAL and
CLKOUT pins for a capacitive load on CLKOUT over the entire process,
temperature ranges, and voltage ranges. For input frequencies greater than 15 MHz
and (MF+1)
£
2, this skew is between -0.9 ns and +0.9 ns. Otherwise, this skew is not
guaranteed. However, for (MF+1)<10 and input frequencies greater than 10 MHz,
the skew is between -2.3ns and +2.3ns.
¥ Phase jitterÑA variation in the skew that occurs between the falling edges of the
EXTAL and CLKOUT pins for a speciÞc temperature, voltage, input frequency, MF,
and capacitive load on the CLKOUT pin. These variations are a result of the PLL
locking mechanism. For input frequencies greater than 15 MHz and (MF+1)
£
2, this
jitter is less than
±
0.6ns. Otherwise, this jitter is not guaranteed. However, for
(MF+1)<10 and input frequencies greater than 10 MHz, this jitter is less than
±
2ns.
Table 15-1. Power-On Reset SPLL Configuration
MODCK [1Ð2] Default MF+1 at Power-On Reset SPLL Options Selected
00 513 OSCCLK (SPLL input) is OSCM
freq
[referred to as 32 KHz Mode].
01 5 OSCCLK (SPLL input) is OSCM
freq
[referred to as 4 MHz Mode].
10 1 OSCCLK (SPLL input) is EXTCLK
freq
11 5 OSCCLK (SPLL input) is EXTCLK
freq