Motorola MPC860 PowerQUICC, User Manual

Page: 740 / 1106

27-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
27.12 SCC BISYNC Receive BD (RxBD)
The CP uses BDs to report on each buffer received. It closes the buffer, generates a
maskable interrupt, and starts receiving data into the next buffer after any of the following:
¥ A user-deÞned control character is received.
¥ An error is detected.
¥ A full receive buffer is detected.
¥ The
ENTER HUNT MODE
command is issued.
¥ The
CLOSE RX BD
command is issued.
Figure 27-6 shows the SCC BISYNC RxBD.
Table 27-11 describes SCC BISYNC RxBD status and control Þelds.
14Ð15 TPM Transmitter parity mode. Selects the type of parity the transmitter performs and can be modiÞed
on-the-ßy. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 E Ñ W I L F CM Ñ DE Ñ NO PR CR OV CD
2 Data Length
4 Rx Data Buffer Pointer
6
Figure 27-6. SCC BISYNC RxBD
Table 27-11. SCC BISYNC RxBD Status and Control Field Descriptions
Bits Name Description
0 E Empty.
0 The buffer is full or stopped receiving because of an error. The core can read or write any Þelds of this
RxBD. The CP does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD.
1 Ñ Reserved, should be cleared.
2 W Wrap (last BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that
RBASE points to. The number of BDs in this table is determined by the W bit and by overall space
constraints of the dual-port RAM.
Table 27-10. PSMR Field Descriptions (Continued)
Bits Name Description