Motorola MPC860 PowerQUICC, User Manual

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17-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
17.2.2 PCMCIA Input Port Signals
The following signals are used by a PCMCIA slot to indicate card status. The MPC860
provides synchronization, transition detection, optional interrupt generation, and the means
for the software to read the signal state. This function is not necessarily speciÞc to
PCMCIA; a system can use these signals as a general-purpose input port with edge
detection and interrupt capability. These signals appear on pins IP_A[0Ð7] and IP_B[0Ð7].
All these signals are symmetrical except IP_x7, which has extended edge detection
capability and IP_x2, which serves as IOIS16_x cycle-control signals for PCMCIA cycles.
ALE_x Address latch enable. Output strobes that control the external latches of the address and REG signals for
the appropriate PC card being accessed. ALE_A is asserted when socket A is accessed and ALE_B is
asserted when socket B is accessed. Note that latches are used when power consumption is an issue.
They keep the PCMCIA signals from toggling unnecessarily when the PCMCIA cards are not being
accessed. If power consumption is not an issue, buffers can be used instead of ALE_x signals.
IOIS16 I/O port is 16 bits. Input. When the card and its socket are programmed for I/O interface operation, this
signal is used as IOIS16_x and must be asserted by the card when the address on the bus corresponds to
an address on the PC card and the I/O port being addressed supports 16-bit accesses. If the I/O region in
which the address resides is programmed as 8 bits wide, IOIS16_x is ignored.
Table 17-2. PCMCIA Input Port Signals
Signal Description
VS1_x,
VS2_x Voltage sense. Input. Used as VS1 and VS2 and generated by PC cards. They notify the socket of the card
V
CC
requirement. These signals are connected to IP_x[0Ð1].
WP Write protect. Input. When the card and socket are programmed for memory interface operation, this
signal is used as WP. It reßects the state of the write-protect switch on the PC card. The PC card must
assert WP when the card switch is enabled. It must be negated when the switch is disabled. For a PC card
that is writable without a switch, WP must be connected to ground. If the PC card is permanently
write-protected, WP must be connected to V
CC
. These signals are connected to IP_x2 pins.
CD1_x,
CD2_x Card detect. Input. Provide proper detection of card insertion. They must be connected to ground internally
on the PC card, thus, these signals are forced low when a card is placed in the socket. These signals must
be pulled up to system V
CC
to allow card detection to function while the card socket is powered down.
These signals are connected IP_x4 and IP_x3, respectively.
BVD1_,
BVD2_ Battery voltage detect. Input. When the card and its socket are programmed for memory interface
operation, these signals are used as BVD1_x and BVD2_x and are generated by PC cards with on-board
batteries to report the battery condition. Both BVD1_x and BVD2_x must be held asserted when the
battery is in good condition. Negating BVD2_x while keeping BVD1_x asserted indicates the battery is in a
warning condition and should be replaced, although data integrity on the card is still assured. Negating
BVD1_x indicates that the battery is no longer serviceable and data is lost, regardless of the state of
BVD2_x. These signals are connected to IP_x6 and IP_x5, respectively.
STSCHG Status change. Input. When the card and its socket are programmed for I/O interface operation, BVD1_x is
used as STSCHG and is generated by I/O PC cards. STSCHG must be held negated when the Òsignal on
changeÓ bit and ÒchangedÓ bit in the card status register on the PC card are either or both zero. STSCHG
must be asserted when both bits = 1.
Table 17-1. PCMCIA Cycle Control Cycles (Continued)
Signal Description