Motorola MPC860 PowerQUICC, User Manual

Page: 269 / 1106

MOTOROLA Chapter 10. Instruction Execution Timing 10-7
Part II. PowerPC Microprocessor Module
10.2.1 Load/Store Instruction Timing
Table 10-2 summarizes load/store instruction timings. This table assumes zero wait-state
memory references on a parked bus and pipelined external memory accesses.
1
Although a store (as well as mtspr for SPRs external to the core) issued to the LSU buffer frees the core
pipeline, the next load or store is not performed on the bus until it is free.
2
See Table 5-5.
3
Refer to Chapter 5, ÒPowerPC Core Register Set.Ó
4
See Section 5.1.1.1.1, ÒCondition Register (CR),Ó and Section 5.1.2.3.1, ÒMachine State Register (MSR).Ó
5
6
Division blockage = division latency
7
Blockage of the multiply instruction is dependent on the next instruction.If the next instruction a divide, the
blockage is 2 clocks; otherwise the blockage is 1 clock. is a multiply, the blockage is 1 clock; if it is
8
Assumes nonspeculative aligned access, on-chip memory, and available bus. See Section 4.5.3.4,
ÒNonspeculative Load Instructions,Ó Section 4.5.3.5, ÒUnaligned Accesses,Ó and Section 10.2.1, ÒLoad/Store
Instruction Timing.Ó
1
N denotes the number of registers transferred.
Memory synchronization: lwarx , stwcx. Ser 2 LSU Yes
Move CR from XER: mcrxr Ser 1 LSU Yes
Move to/from SPR (Debug, DAR, DSISR): mtspr , mfspr Ser 1 LSU Yes
String instructions: lswi , lswx , stswi , stswx . See
Section 10.2.2, ÒString Instruction Latency.Ó
Ser 1 + no. of words
accessed LSU Yes
Memory control instructions: isync Serialize BPU Yes
Order memory access: eieio 1 LSU Next load/store
is synchronized
with ones before
Cache control: icbi 1 LSU,
I-cache No
Table 10-2. Load/Store Instructions Timing
Instruction Type
Latency Cleared from LSU
Data Cache External Memory Data Cache External Memory
Integer single target register load (aligned) 2 cycles 5 cycles 2 cycles 5 cycles
Integer single target register store (aligned) 1 cycle 1 cycle 2 cycles 5 cycles
Load/store multiple 1 + N
1
1 + N
Table 10-1. Instruction Execution Timing (Continued)
Instructions Latency Blockage Unit Serializing
Where
DivisionLatency
NoOverflow 3
Þ
34 divisorLength Ð
4
------------------------------------------------------
è
æ
+
Overflow 2
Þ
--------------------------------------------------------------------------------------------------------------------- =
Overflow
x
0
---
è ø
æ ö
or
MaxNegativeNumber
1 Ð
---------------------------------------------------------------
è ø
æ ö
=
3 N
N 1 +
3
--------------
è ø
æ ö
+ + 3 N
N 1 +
3
--------------
è ø
æ ö
+ +