Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 5. PowerPC Core Register Set 5-1
Chapter 5
PowerPC Core Register Set
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This chapter describes the software-accessible registers implemented on the MPC860.
These include registers that are deÞned by the PowerPC architecture and registers that are
speciÞc to the MPC860. This section does not include registers that are part of the
communication processor module (CPM); these registers are described in Part V, ÒThe
Communications Processor Module.Ó Refer to the PowerPC Family: The Programming
Environments for 32-Bit Microprocessors
for more information about the PowerPC
architectureÕs register deÞnition.
5.1 MPC860 Register Implementation
Registers implemented in the MPC860 core can be grouped as follows:
¥ Registers deÞned by the PowerPC architecture. There are two types of PowerPC
registers.
Ñ User registers, which can be accessed by user-level software. All PowerPC
user-level registers are deÞned by the user instruction set architecture (UISA)
except for the time base registers, which can be read by user-level software and
are deÞned by the virtual environment architecture (VEA). User registers are
described in Section 5.1.1, ÒPowerPC RegistersÑUser Registers.Ó
Ñ Supervisor registers, which can be accessed by supervisor software and in some
cases are the automatic result of hardware activity, such as when an exception is
taken and when the system is reset. All supervisor registers are deÞned by the
operating environment architecture (OEA), except the time base registers, which
can be written to only by supervisor software and are deÞned by the VEA.
PowerPC supervisor registers are described in Section 5.1.2, ÒPowerPC
RegistersÑSupervisor Registers.Ó
The UISA, VEA, and OEA architecture deÞnitions are described in Section 4.1.1,
ÒLevels of the PowerPC Architecture.Ó
¥ MPC860-speciÞc registers. These registers are either supervisor-level registers or
debug registers. These are described brießy in Section 5.1.3, ÒMPC860-SpeciÞc
SPRs,Ó but are described thoroughly in later chapters. Table 5-9 and Table 2-1
provide cross references to the sections in this book where each register is described.