MOTOROLA
Chapter 4. The PowerPC Core
4-13
Part II. PowerPC Microprocessor Module
The nonspeculative identiÞcation relates to the state of the cycleÕs associated instruction.
For lmw, although the accesses are pipelined into the bus, they are all marked as
nonspeculative because the instruction is nonspeculative. If a single-register load
instruction generates more than one bus cycle, some of the cycles can be marked as
speculative and later cycles can be marked as nonspeculative after all prior instructions end.
Speculative load accesses to external memory marked nonspeculative cannot occur until the
load instruction becomes nonspeculative.
4.5.3.5 Unaligned Accesses
Although the 32-bit U-bus supports only naturally aligned transfers, the LSU supports
unaligned accesses in hardware by breaking them into a pipelined series of aligned
transfers. Table 4-2 shows the number of bus cycles needed for single-register load/store
accesses.
4.5.3.6 Atomic Update Primitives
The lwarx and stwcx. instructions are atomic update primitives and are used to set and clear
memory reservations. Reservation accesses made by the same processor are implemented
by the LSU. The external bus interface implements memory reservations as they relate to
accesses made by external bus devices. Accesses made by other internal devices to internal
memories implement memory reservations as they relate to special internal bus snoop logic.
Table 4-2. Bus Cycles Needed for Single-Register Load/Store Accesses
Transfer Size
Transfer Address (Last Two Bits)
Number of Bus Cycles
Transfer Type
Address/Size
Byte
0x00
1
Aligned
0x00/byte
0x01
1
Aligned
0x01/byte
0x02
1
Aligned
0x02/byte
0x03
1
Aligned
0x03/byte
Half Word
0x00
1
Aligned
0x00/halfword
0x01
2
Unaligned
0x01/byte
0x02/byte
0x02
1
Aligned
0x02/halfword
0x03
2
Unaligned
0x03/byte
0x04/byte
Word
0x00
1
Aligned
0x00/word
0x01
3
Unaligned
0x01/byte
0x02/halfword
0x05/byte
0x02
2
Unaligned
0x02/halfword
0x04/halfword
0x03
3
Unaligned
0x03/byte
0x04/halfword
0x06/byte
Summary of Contents for MPC860 PowerQUICC
Page 3: ...MPC860UM AD 07 98 REV 1 MPC860 PowerQUICC ª UserÕs Manual ...
Page 36: ...xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 114: ...3 16 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
Page 262: ...9 36 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
Page 320: ...12 12 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
Page 326: ...IV vi MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...
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Page 530: ...17 26 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...
Page 632: ...21 44 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
Page 660: ...22 28 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
Page 1024: ...B 8 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
Page 1030: ...C 6 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
Page 1086: ...Glossary 12 MPC860 PowerQUICC UserÕs Manual MOTOROLA ...
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