32-6
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part V. The Communications Processor Module
An MPC860 I
2
C controller attempting a master read request could simultaneously be
targeted for an external master write (slave read). Both operations trigger the controllerÕs
I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which
operation caused the interrupt, software must verify that its transmit operation actually
completed before assuming that the received data is the result of its read operation.
Problems could also arise if the MPC860's I
2
C controller master sets up a transmit buffer
and BD for a write request, but then is the target of a read request from another master.
Without software precautions, the I
2
C controller responds to the other master with the
transmit buffer originally intended for its own write request. To avoid this situation, a
higher-level handshake protocol must be used. For example, a master, before reading a
slave, writes the slave with a description of the requested data (which register should be
read, for example). This operation is typical with many I
2
C devices.
32.4 I
2
C Registers
The following sections describe the I
2
C registers.
32.4.1 I
2
C Mode Register (I2MOD)
The I
2
C mode register, shown in Figure 32-6, controls the I
2
C modes and clock source.
Table 32-1 describes I2MOD bit functions.
Bit
0
1
2
3
4
5
6
7
Field
Ñ
REVD
GCD
FLT
PDIV
EN
Reset
0000_0000
R/W
R/W
Addr
0x860
Figure 32-6.I
2
C Mode Register (I2MOD)
Table 32-1. I2MOD Field Descriptions
Bits Name
Description
0Ð1
Ñ
Reserved and should be cleared.
2
REVD Reverse data. Determines the Rx and Tx character bit order.
0 Normal operation. The msb of a character is transferred Þrst.
1 Reverse data. The lsb of a character is transferred Þrst.
3
GCD
General call disable. Determines whether the receiver acknowledges a general call address.
0 General call address is enabled.
1 General call address is disabled.
4
FLT
Clock Þlter. Determines if the I
2
C input clock SCL is Þltered to prevent spikes in a noisy environment.
0 SCL is not Þltered.
1 SCL is Þltered by a digital Þlter.
Summary of Contents for MPC860 PowerQUICC
Page 3: ...MPC860UM AD 07 98 REV 1 MPC860 PowerQUICC ª UserÕs Manual ...
Page 36: ...xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 114: ...3 16 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
Page 262: ...9 36 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
Page 326: ...IV vi MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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