Motorola MPC860 PowerQUICC, User Manual

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8-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
The MPC860 instruction cache includes the following operational features:
¥ Instruction fetch latency is reduced by sending the requested instruction address to
the instruction cache and internal bus simultaneously. A cache hit aborts the internal
bus transaction before the MPC860 can initiate an external fetch.
¥ The instruction cache supports stream hits (allows fetching from the burst buffer or
directly from the internal data bus, before the instruction cache array is Þlled)
¥ The instruction cache supports hits under misses (allows servicing hits while a
previous miss is being fetched from the external bus)
¥ A fetch request from the instruction sequencer has priority over burst buffer writes
to the cache array (the burst buffer holds the last missed cache block), thus
increasing the overall performance
¥ EfÞciently uses the pipeblock of the internal data bus by initiating a new burst cycle
(if miss is detected) while bringing the tail of the previous missed block
¥ Performance for caching-inhibited regions is enhanced by fetching a full 4-word
block into the burst buffer. Instructions in the burst buffer are only used once before
being refetched
8.5.1 Instruction Cache Hit
In the case of a cache hit, the cache block is transferred to the cache block buffer and
forwarded to the stream hit multiplexer and word select multiplexer. As shown in
Figure 8-2, bits 28Ð29 of the instruction address are used to select one word of the cache
block which is transferred to the instruction sequencer in the core.
8.5.2 Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal
bus with a 4-word burst transfer read request. The transfer begins with the word requested
by the instruction sequencer (critical-word Þrst), followed by the remaining words (if any)
of the cache block, then by any remaining words at the beginning of the block
(wrap-around).
On a cache miss, the critical word is simultaneously written to the burst buffer and
forwarded to the instruction sequencer, thus minimizing stalls due to cache Þll latency. As
subsequent words are received from the internal bus, they are also written into the burst
buffer and delivered to the instruction sequencer either directly from the internal bus or
from the burst buffer (a stream hit). A cache block in the array is then selected to receive
the cache block being gathered in the burst buffer. The selection algorithm gives Þrst
priority to invalid blocks. If both blocks in the set are marked invalid, the block in way 0 is
selected. If neither of the two blocks in the selected set are invalid, then the least recently
used block is selected for replacement. Locked cache blocks are never replaced.
The instruction cache is not blocked to internal accesses while the fetch (caused by a cache
miss) completes. This functionality is sometimes referred to as Ôhits under misses,Õ because