363-206-285
Circuit Pack Descriptions
Issue 3
June 2001
7-37
The framer circuit acquires frame information (either SF or ESF) from the DS1
signal and sends the information to the PM processor. The PM processor then
generates near-end and far-end (ESF only) DS1 PM parameters. When
provisioned for DS1 clear channel, no PM path parameters are generated.
Timing Circuitry
7
The timing distribution to the DS1PM contains ten timing signals: two high-speed
clocks (active and standby), four VT-G clocks (two active and two standby), and
four frame sync signals (two active and two standby).
The DS1PM receives from the MXRVO/STS1E an STS-1 rate high-speed clock
that provides the frequency reference for the desynchronizing phase-locked loop.
This high-speed reference clock is also used to synthesize the DS1 rate AIS clock
source for the DS1 devices and to provide a DS1 test signal.
The DS1PM uses the VT-G clocks (6.912 MHz) and the frame sync signals it
receives from the MXRVO/STS1E to clock VT-G data to/from the MXRVO/STS1E.
Protection Circuitry
7
Optional 1x7 revertive DS1PM circuit pack protection is provided, and this
protection is independent of the MXRVO/STS1E circuit pack(s). The DS1PM
protection switch points are implemented with on-board relays on the DSX-1 side
and with logic selectors at the VT-G level on the active and standby MXRVO/
STS1E circuit packs. The SYSCTL controls these relays through two serial
interfaces so that a failure of one serial interface to the DS1PM does not prevent
control of the relays. If +5 V power on the DS1PM fails, the relays default to the
protection state. If the SYSCTL is removed, the relays remain in their current
state.
Shorting contacts are provided in the DS1PM backplane connector so that when
the circuit pack is removed, the DSX-1 cable pairs short through to the protection
bus.
!
CAUTION:
Unused low-speed interface slots within a partially equipped group must be
equipped with 177A Retainer cards if DS1PM protection is used. Failure to
do so may result in corrupted transmission. The BBF3 DS1PM circuit pack
can be mixed with the BBF1/1B. If mixed, the protection circuit pack must be
a BBF3 DS1PM. Failure to do so may result in loss of transmission.
When a DS1PM circuit pack is inserted, the relays are in the protection state until
the SYSCTL determines that the circuit pack is good.
Summary of Contents for DDM-2000 OC-3
Page 4: ......
Page 14: ...xiv Issue 3 June 2001 Contents GL Glossary GL 1 ...
Page 24: ...xxiv Issue 3 June 2001 Figures ...
Page 28: ...Tables xxviii Issue 3 June 2001 A A SONET Overview A 34 SONET Transport Rates A 20 ...
Page 58: ...363 206 285 About This Document lviii Issue 3 June 2001 ...
Page 60: ...1 ii Issue 3 June 2001 Table of Contents ...
Page 80: ...363 206 285 System Introduction 1 20 Issue 3 June 2001 ...
Page 154: ...3 ii Issue 3 June 2001 Table of Contents ...
Page 184: ...4 ii Issue 3 June 2001 Table of Contents ...
Page 252: ...363 206 285 Transmission and Synchronization Interfaces 5 60 Issue 3 June 2001 ...
Page 254: ...6 ii Issue 3 June 2001 Table of Contents ...
Page 278: ...7 vi Issue 3 June 2001 Table of Contents ...
Page 436: ...363 206 285 Circuit Pack Descriptions 7 158 Issue 3 June 2001 ...
Page 440: ...8 iv Issue 3 June 2001 Table of Contents ...
Page 518: ...363 206 285 Administration and Provisioning 8 78 Issue 3 June 2001 ...
Page 588: ...10 iv Issue 3 June 2001 Table of Contents ...
Page 690: ...363 206 285 Commands and Reports 11 20 Issue 2 February 2000 ...
Page 1252: ...11 582 2000 February 2 Issue OC 3 DDM 2000 ...
Page 1254: ...A ii Issue 3 June 2001 Table of Contents ...
Page 1276: ...363 206 285 A SONET Overview A 22 Issue 3 June 2001 ...
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Page 1348: ...363 206 285 Acceptance IXL 001 Issue 3 June 2001 Page 2 of 2 DDM 2000 OC 3 MULTIPLEXER ...
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