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6 Memory
6.3 Flash Cgg-Vcg: Flash memory cell Gate capacitance (A.01.11)
[Supported Analyzer]
B1500A
[Description]
Measures the Gate capacitance (Cgg), and plots the Cgg-Vcs characteristics.
DC bias output is performed from -VcsStart to -VcsStop in -VcsStep steps.
For a more accurate measurement, perform correction data measurement at the measurement frequency before
starting the capacitance measurement.
If the measurement frequency is not included in the list of default frequencies below, click the Advanced
Options... button and set the measurement frequency on the Frequency area of the Advanced Options for CMU
Calibration window.
Default frequencies:
1 k, 2 k, 5 k, 10 k, 20 k, 50 k, 100 k, 200 k, 500 k, 1 M, 1.2 M, 1.5 M, 2 M, 2.5 M, 2.7 M, 3 M, 3.2 M, 3.5 M,
3.7 M, 4 M, 4.2 M, 4.5 M, 5 MHz
[Device Under Test]
Flash memory cell
Open the Floating Gate, and connect the Control Gate to CMU Low and the other terminals to CMU High.
[Device Parameters]
Lg: Gate length
Wg: Gate width
Temp: Temperature
M: Number of cells connected in parallel. M=1 for the single cell.
[Test Parameters]
IntegTime: Integration time
FREQ: Measurement frequency
OscLevel: Measurement signal level
ControlGate: CMU connected between Control Gate and Substrate (CV sweep measurement)
VcsStart: DC bias start voltage
VcsStop: DC bias stop voltage
VcsStep: DC bias step voltage
[Extended Test Parameters]
HoldTime: Hold time
DelayTime: Delay time
[Measurement Parameters]
Parallel capacitance Cp
Conductance G
[User Function]
PI=3.141592653589
D=G/(2*PI*FREQ*Cp)
Rp=1/G
Cs=(1+D^2)*Cp
X=-1/(2*PI*FREQ*Cs)
Rs=D*abs(X)
Z=sqrt(Rs^2+X^2)
Theta=atan(X/Rs)
Agilent EasyEXPERT Application Library Reference, Edition 8
6-8