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RX610 Group

15. 16-Bit Timer Pulse Unit (TPU)

R01UH0032EJ0120 Rev.1.20

Page 522 of 1006

Feb 20, 2013

15.9.8

Conflict between TPUm.TGRy Read and Input Capture

If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture
transfer.

Figure 15.48 shows the timing in this case.

Internal data bus

TGRy

PCLK

Input capture signal

Buffer register read by CPU

M

N

N

Figure 15.48 Conflict between TPUm.TGRy Read and Input Capture

15.9.9

Conflict between TPUm.TGRy Write and Input Capture

If the input capture signal is generated in a TGRy write cycle, the input capture operation takes precedence and the write
to TGRy is not performed. Figure 15.49 shows the timing in this case.

TCNT write by CPU

TCNT

TGRy

PCLK

Input capture signal

M

M

Figure 15.49 Conflict between TPUm.TGRy Write and Input Capture

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Summary of Contents for RX600 Series

Page 1: ...these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com ...

Page 2: ...e range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as t...

Page 3: ...s supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provi...

Page 4: ...all points to note into account Points to note are given in their contexts and at the final part of each section and in the section giving usage notes The list of revisions is a summary of major points of revision or addition for earlier versions It does not cover all revised items For details on the revised points see the actual locations in the manual Document Type Contents Document Title Docume...

Page 5: ...egisters R The bit or field is readable Writing to this bit or field has no effect 2 Reserved Make sure to use the specified value when writing to this bit or field otherwise the correct operation is not guaranteed 3 Setting prohibited The correct operation is not guaranteed if such a setting is performed Address xxxx xxxxxh b7 b6 b5 b4 b3 b2 b1 b0 Value after reset x 0 0 0 0 0 0 0 Bit Symbol Bit ...

Page 6: ...y Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi Z High Impedance IEBus Inter Equipment Bus I O Input Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non Connect PLL Phase Locked Loop PWM Pulse Width Modulation SIM Subscriber Identity Module UART Universal Asynchronous Receiver Transmitt...

Page 7: ... 2 2 2 3 Program Counter PC 57 2 2 2 4 Processor Status Word PSW 58 2 2 2 5 Backup PC BPC 60 2 2 2 6 Backup PSW BPSW 60 2 2 2 7 Fast Interrupt Vector Register FINTV 60 2 2 2 8 Floating Point Status Word FPSW 61 2 2 2 9 Accumulator ACC 64 2 3 Processor Mode 65 2 3 1 Supervisor Mode 65 2 3 2 User Mode 65 2 3 3 Privileged Instruction 65 2 3 4 Switching Between Processor Modes 65 2 4 Data Types 66 2 4...

Page 8: ...nstruction Processing Time 86 2 8 4 Numbers of Cycles for Response to Interrupts 87 3 Operating Modes 88 3 1 Operating Mode Types and Selection 88 3 2 Register Descriptions 89 3 2 1 Mode Monitor Register MDMONR 89 3 2 2 Mode Status Register MDSR 90 3 2 3 System Control Register 0 SYSCR0 91 3 2 4 System Control Register 1 SYSCR1 93 3 3 Details of Operating Modes 94 3 3 1 Single Chip Mode 94 3 3 2 O...

Page 9: ...7 3 2 External Clock Input 165 7 4 PLL Circuit 165 7 5 Frequency Divider 165 7 6 Internal Clock 166 7 6 1 System Clock ICLK 166 7 6 2 Peripheral Module Clock PCLK 166 7 6 3 External Bus Clock BCLK 166 7 7 Usage Notes 167 7 7 1 Notes on the Clock Generation Circuit 167 7 7 2 Notes on Resonator 168 7 7 3 Notes on Board Design 168 8 Low Power Consumption 169 8 1 Overview 169 8 2 Register Descriptions...

Page 10: ...oftware Standby Mode 195 8 5 4 1 Transition to Deep Software Standby Mode 195 8 5 4 2 Canceling Deep Software Standby Mode 196 8 5 4 3 Pin States when Deep Software Standby Mode is Canceled 196 8 5 4 4 Setting Oscillation Settling Time after Deep Software Standby Mode is Canceled 197 8 5 4 5 Example of Deep Software Standby Mode Application 198 8 5 4 6 Flowchart to Use Deep Software Standby Mode 1...

Page 11: ...t Request Register i IRi i interrupt vector number 223 10 2 2 Interrupt Request Destination Setting Register i ISELRi i interrupt vector number 225 10 2 3 Interrupt Request Enable Register m IERi i 02h to 1Fh 226 10 2 4 Interrupt Priority Register i IPRi i 00h to 8Fh 227 10 2 5 Fast Interrupt Register FIR 228 10 2 6 IRQ Detection Enable Register n IRQERn n 0 to 15 229 10 2 7 IRQ Control Register n...

Page 12: ... Buses 256 11 1 Overview 256 11 2 Description of Buses 257 11 2 1 CPU Buses 257 11 2 2 Internal Main Buses 257 11 2 3 Internal Peripheral Buses 258 11 2 4 External Bus 258 11 2 5 Parallel Operation 260 11 3 Register Descriptions 261 11 3 1 CSi Control Register CSiCNT i 0 to 7 263 11 3 2 CSi Recovery Cycle Register CSiREC i 0 to 7 265 11 3 3 CSi Mode Register CSiMOD i 0 to 7 267 11 3 4 CSi Wait Con...

Page 13: ...er DMMOD 305 12 2 2 DMA Control Register A DMCRA 307 12 2 3 DMA Control Register B DMCRB 310 12 2 4 DMA Control Register C DMCRC 311 12 2 5 DMA Control Register D DMCRD 312 12 2 6 DMA Control Register E DMCRE 313 12 2 7 DMA Current Transfer Source Address Register DMCSA 314 12 2 8 DMA Current Transfer Destination Address Register DMCDA 315 12 2 9 DMA Current Transfer Byte Count Register DMCBC 316 ...

Page 14: ... Destination Address Register DAR 339 13 2 5 DTC Transfer Count Register A CRA 340 13 2 6 DTC Transfer Count Register B CRB 341 13 2 7 DTC Control Register DTCCR 341 13 2 8 DTC Vector Base Register DTCVBR 342 13 2 9 DTC Address Mode Register DTCADMOD 343 13 2 10 DTC Module Start Register DTCST 343 13 3 Sources of Activation 344 13 3 1 Allocating Transfer Data and DTC Vector Table 344 13 3 2 Startu...

Page 15: ...er PCR 382 14 2 6 Open Drain Control Register ODR 383 14 2 7 Port Function Control Register0 PFCR0 383 14 2 8 Port Function Control Register 1 PFCR1 384 14 2 9 Port Function Control Register 2 PFCR2 386 14 2 10 Port Function Control Register 3 PFCR3 387 14 2 11 Port Function Control Register 4 PFCR4 388 14 2 12 Port Function Control Register 5 PFCR5 389 14 2 13 Port Function Control Register 6 PFC...

Page 16: ...egister TCR 463 15 2 2 Timer Mode Register TMDR 467 15 2 3 Timer I O Control Register TIORH TIORL TIOR 469 15 2 4 Timer Interrupt Enable Register TIER 479 15 2 5 Timer Status Register TSR 481 15 2 6 Timer Counter TCNT 482 15 2 7 Timer General Register A TGRA Timer General Register B TGRB Timer General Register C TGRC Timer General Register D TGRD 482 15 2 8 Timer Start Register TSTRA TSTRB 483 15 ...

Page 17: ...Write and Overflow Underflow 524 15 9 13 Multiplexing of I O Pins 524 16 Programmable Pulse Generator PPG 525 16 1 Overview 525 16 2 Register Descriptions 529 16 2 1 PPG Trigger Select Register PTRSLR 530 16 2 2 Next Data Enable Registers H and L NDERH NDERL 531 16 2 3 Output Data Registers H and L PODRH PODRL 535 16 2 4 Next Data Registers H and L NDRH NDRL 537 16 2 5 PPG Output Control Register ...

Page 18: ...ow Interrupt Flag Setting to 1 579 17 5 Operation with Cascaded Connection 580 17 5 1 16 Bit Count Mode 580 17 5 2 Compare Match Count Mode 580 17 6 Interrupt Sources 581 17 6 1 Interrupt Sources and DTC Activation 581 17 6 2 A D Converter Activation 581 17 7 Usage Notes 582 17 7 1 Module Stop State Setting 582 17 7 2 Notes on Setting Cycle 582 17 7 3 Conflict between TCNT Write and Counter Clear ...

Page 19: ...er CMCOR 596 19 Watchdog Timer WDT 597 19 1 Overview 597 19 2 Register Descriptions 599 19 2 1 Timer Counter TCNT 599 19 2 2 Timer Control Status Register TCSR 600 19 2 3 Reset Control Status Register RSTCSR 601 19 2 4 Write Window A Register WINA 602 19 2 5 Write Window B Register WINB 602 19 3 Operation 603 19 3 1 Watchdog Timer Mode 603 19 3 2 Interval Timer Mode 604 19 4 Interrupt Source 604 1...

Page 20: ...zation Clock Synchronous Mode 653 20 4 3 Serial Data Transmission Clock Synchronous Mode 654 20 4 4 Serial Data Reception Clock Synchronous Mode 656 20 4 5 Simultaneous Serial Data Clock Synchronous Mode 658 20 5 Operation in Smart Card Interface Mode 660 20 5 1 Sample Connection 660 20 5 2 Data Format Except in Block Transfer Mode 661 20 5 3 Block Transfer Mode 662 20 5 4 Receive Data Sampling Ti...

Page 21: ...Bus Control Register 2 ICCR2 695 22 2 3 I2 C Bus Mode Register 1 ICMR1 699 22 2 4 I2 C Bus Mode Register 2 ICMR2 701 22 2 5 I2 C Bus Mode Register 3 ICMR3 703 22 2 6 I2 C Bus Function Enable Register ICFER 706 22 2 7 I2 C Bus Status Enable Register ICSER 708 22 2 8 I2 C Bus Interrupt Enable Register ICIER 710 22 2 9 I2 C Bus Status Register 1 ICSR1 712 22 2 10 I2 C Bus Status Register 2 ICSR2 716 ...

Page 22: ...9 2 Function to Detect Loss of Arbitration during NACK Transmission NALE Bit 759 22 9 3 Slave Arbitration Lost Detection SALE Bit 760 22 10 Start Condition Restart Condition Stop Condition Issuing Function 761 22 10 1 Issuing a Start Condition 761 22 10 2 Issuing a Restart Condition 761 22 10 3 Issuing a Stop Condition 762 22 11 Bus Hanging 763 22 11 1 Timeout Detection Function 763 22 11 2 Extra ...

Page 23: ...6 23 3 6 Activation by the Compare Match Input Capture A Signals from TPU0 to TPU5 797 23 3 7 Activation on Compare Match of TMR Units 798 23 4 Interrupt Source 799 23 5 A D Conversion Accuracy Definitions 799 23 6 Usage Notes 801 23 6 1 Module Stop Function Setting 801 23 6 2 Notes on Disabling A D Conversion 801 23 6 3 Notes on Restarting A D Conversion 801 23 6 4 Notes on Entering Power Down St...

Page 24: ...ess Error Interrupt Enable Register FAEINT 825 26 2 4 FCU RAM Enable Register FCURAME 826 26 2 5 Flash Status Register 0 FSTATR0 827 26 2 6 Flash Status Register 1 FSTATR1 830 26 2 7 Flash Ready Interrupt Enable Register FRDYIE 831 26 2 8 Flash P E Mode Entry Register FENTRYR 832 26 2 9 Flash Protection Register FPROTR 835 26 2 10 Flash Reset Register FRESETR 836 26 2 11 FCU Command Register FCMDR...

Page 25: ... State 879 26 10 6 ID Code Wait State 893 26 10 7 Programming Erasure Host Command Wait State 894 26 11 ID Code Protection on Connection of the On Chip Debugger 903 26 12 ROM Code Protection 904 26 13 Usage Notes 905 27 Data Flash Flash Memory for Data Storage 907 27 1 Overview 907 27 2 Register Descriptions 909 27 2 1 Flash Mode Register FMODR 910 27 2 2 Flash Access Status Register FASTAT 911 27...

Page 26: ...ns 938 28 2 1 Instruction Register JTIR 939 28 2 2 Bypass Register JTBPR 939 28 2 3 Boundary Scan Register JTBSR 939 28 2 4 IDCODE Register JTID 948 28 3 Operations 949 28 3 1 TAP Controller 949 28 3 2 List of Commands 950 28 4 Usage Notes 952 29 Electrical Characteristics 954 29 1 Absolute Maximum Ratings 954 29 2 DC Characteristics 955 29 3 AC Characteristics 958 29 3 1 Clock Timing 958 29 3 2 C...

Page 27: ...Appendix 1 Port States in Each Processing Mode 980 Appendix 2 Package Dimensions 985 REVISION HISTORY 987 ...

Page 28: ...by instructions with lengths that are variable in byte units and by an enhanced range of addressing modes Timers serial communication interfaces I2 C bus interfaces an A D converter and a D A converter are incorporated as peripheral functions which are essential to embedded devices Facilities for connecting external memory are also included enabling direct connection to memory and peripheral LSI c...

Page 29: ...oint Data types and floating point exceptions conforming to the IEEE754 standard Memory Flash Flash capacity 2 Mbytes max Three types of on board programming modes SCI boot mode user program mode and user boot mode RAM RAM capacity 128 Kbytes Data flash Data flash capacity 32 Kbytes MCU operating modes Single chip mode on chip ROM enabled extended mode and on chip ROM disabled extended mode Clock ...

Page 30: ...enabled I O ports Programmable I O ports I O pins 117 144 pin LQFP 140 176 pin LFBGA Pull up resistors 40 Open drain outputs 16 5 V tolerance 10 Timer 16 bit timer pulse unit 16 bits x 6 channels x 2 units Up to 16 pulse inputs and outputs Select from among 7 or 8 counter input clocks for each channel Input capture output compare function Maximum of 15 phase PWM output poss ble in PWM mode Buffere...

Page 31: ...ion Conversion time 1 0 µs per channel at 50 MHz PCLK operation Two kinds of operating modes Single mode and scan mode single scan mode or continuous scan mode Sample and hold function Three types of A D conversion start Conversion can be started by software a conversion start trigger by the timer TPU or TMR or an external trigger signal D A converter 2 channels 10 bit resolution Output voltage 0 ...

Page 32: ...0144KA A 1 5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F56107VDFP PLQP0144KA A 1 5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F56107WNBG PLBG0176GA A 1 5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F56107WDBG PLBG0176GA A 1 5 Mbytes 128 Kbytes 32 Kbytes 100 MHz R5F56106VNFP PLQP0144KA A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz R5F56106VDFP PLQP0144KA A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz R5F56106WNBG PLBG0176GA A 1...

Page 33: ...r of pins V 144 pins W 176 pins Indicates a Renesas semiconductor product Indicates the type of memory F Flash memory version Indicates the RX600 Series Indicates the RX610 Group R Indicates a Renesas MCU Indicates the ROM capacity RAM capacity and data flash capacity 8 2 Mbytes 128 Kbytes 32 Kbytes 7 1 5 Mbytes 128 Kbytes 32 Kbytes 6 1 Mbyte 128 Kbytes 32 Kbytes 4 768 Kbytes 128 Kbytes 32 Kbytes ...

Page 34: ...nnels unit 1 SCI 7 channels WDT RIIC 2 channels Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Clock generation circuit Data flash CRC Internal main bus 2 Internal main bus 1 Operand bus CMT 2 channels unit 0 Legend ICU Interrupt control unit DTC Data transfer controller DMAC DMA controller BSC Bus controller WDT Watchdog timer CRC CRC Cycl...

Page 35: ...PA1 PA0 PA2 MDE VCL MD0 MD1 PA5 PA4 PA6 P86 P85 XTAL RES PH1 PH0 VSS VSS EXTAL NMI VCC P70 VCC P71 P34 PF6 PF4 PF5 P74 P73 PB1 P33 P32 P30 P31 PB3 PB4 PB5 PF0 PF3 PF1 PF2 PB6 PC0 VSS PC7 PH4 P51 P81 P83 P57 P37 P14 VSS VCC P26 P27 PC1 PC2 PH2 P76 VSS P50 P80 VSS P56 P36 P12 P16 P20 P24 P25 VCC PC4 PC6 P77 VCC PH6 P52 VCC P54 P84 P11 P15 PLLVCC P22 P23 PE0 PD6 PD4 P63 P60 PD1 PG2 P97 P93 P90 P46 P4...

Page 36: ...OCB2 TCLKD A P10 IRQ0 B P11 SCK2 IRQ1 B P12 RxD2 IRQ2 B P13 TxD2 ADTRG0 IRQ3 B P14 TCLKA B SDA1 IRQ4 B P15 TCLKB B SCK3 SCL1 IRQ5 B PLLVSS P16 TCLKC B RxD3 SDA0 IRQ6 B PLLVCC P20 PO0 TIOCA3 TIOCB3 TMRI0 TxD0 PC5 A21 SCK5 CS5 D P82 TRCLK P17 TCLKD B TxD3 SCL0 ADTRG1 IRQ7 B PE1 D9 PE3 D11 PE4 D12 PE5 D13 IRQ5 A PE6 D14 IRQ6 A PE7 D15 IRQ7 A PA0 A0 BC0 PO16 TIOCA6 PA1 A1 PO17 TIOCA6 TIOCB6 PA2 A2 PO1...

Page 37: ...CK0 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PC4 A20 PC6 A22 RxD5 CS6 D PC7 A23 TxD5 CS4 D CS7 D P75 P76 IRQ14 A P77 P50 WR0 WR P51 WR1 BC1 P52 RD P53 BCLK P80 P81 TRSYNC VCC VSS P83 P54 TRDATA0 P55 TRDATA1 P56 TRDAT...

Page 38: ...C A3 VREFL A4 P43 IRQ11 B AN3 A5 P46 IRQ14 B AN6 A6 P90 AN8 A7 P93 AN11 A8 P97 AN15 A9 PG2 A10 PD1 D1 A11 P60 CS0 CS4 A CS5 B A12 P63 CS3 A CS7 A A13 PD4 D4 A14 PD6 D6 A15 PE0 D8 B1 P67 DA1 B2 P05 IRQ13 A TMO3 RxD4 TCK B3 VREFH B4 P42 IRQ10 B AN2 B5 P45 IRQ13 B AN5 B6 VCC B7 P92 AN10 B8 P96 AN14 B9 PG1 B10 PD0 D0 B11 P61 CS1 CS2 B CS5 A CS6 B CS7 B B12 VCC B13 PD5 D5 B14 PE1 D9 B15 PE2 D10 C1 P02 ...

Page 39: ... PG3 C10 PD2 D2 C11 P62 CS2 A CS6 A C12 VSS C13 PD7 D7 C14 PE3 D11 C15 PE5 IRQ5 A D13 D1 P65 IRQ15 A D2 P01 IRQ9 A TMCI2 RxD6 D3 AVSS D4 P40 IRQ8 B AN0 D5 P44 IRQ12 B AN4 D6 P91 AN9 D7 P95 AN13 D8 PG0 D9 PG4 D10 PD3 D3 D11 P64 CS4 B D12 PE4 D12 D13 PE6 IRQ6 A D14 D14 PE7 IRQ7 A D15 D15 PG5 E1 VSS E2 WDTOVF TDO E3 EMLE E4 P00 IRQ8 A TMRI2 TxD6 E12 VCC E13 PG7 E14 PG6 E15 VSS F1 MD1 F2 MD0 F3 VCL F4...

Page 40: ...GA F13 PA2 A2 PO18 TIOCC6 TCLKE F14 PA0 A0 BC0 PO16 TIOCA6 F15 PA1 A1 PO17 TIOCA6 TIOCB6 G1 RES G2 XTAL G3 P85 G4 P86 G12 PA7 A7 PO23 TIOCA8 TIOCB8 TCLKH G13 PA6 A6 PO22 TIOCA8 G14 PA4 A4 PO20 TIOCA7 G15 PA5 A5 PO21 TIOCA7 TIOCB7 TCLKG H1 VCC H2 NMI H3 EXTAL H4 VSS H12 PB0 A8 PO24 TIOCA9 H13 VSS H14 PH0 H15 PH1 J1 PF5 J2 PF4 J3 PF6 J4 P34 IRQ4 A PO12 TIOCA1 J12 P72 J13 P71 CS4 C CS5 C CS6 C CS7 C ...

Page 41: ... PO9 TIOCA0 TIOCB0 K2 P30 IRQ0 A PO8 TIOCA0 K3 P32 IRQ2 A PO10 TIOCC0 TCLKA A K4 P33 IRQ3 A PO11 TIOCC0 TIOCD0 TCLKB A K12 PB2 A10 PO26 TIOCC9 K13 PB1 A9 PO25 TIOCA9 TIOCB9 K14 P73 K15 P74 ADTRG3 L1 PF2 L2 PF1 L3 PF3 L4 PF0 L12 PB7 A15 PO31 TIOCA11 TIOCB11 L13 PB5 A13 PO29 TIOCA10 TIOCB10 L14 PB4 A12 PO28 TIOCA10 L15 PB3 A11 PO27 TIOCC9 TIOCD9 M1 P27 PO7 TIOCA5 TIOCB5 SCK1 M2 P26 PO6 TIOCA5 TMO1 T...

Page 42: ...CLKD A M7 P57 WAIT TRDATA3 M8 P83 M9 P81 TRSYNC M10 P51 WR1 BC1 M11 PH4 M12 PC7 A23 CS4 D CS7 D TxD5 M13 VSS M14 PC0 A16 M15 PB6 A14 PO30 TIOCA11 N1 P25 PO5 TIOCA4 TMCI1 RxD1 N2 P24 PO4 TIOCA4 TIOCB4 TMRI1 N3 P20 PO0 TIOCA3 TIOCB3 TMRI0 TxD0 N4 P16 IRQ6 B TCLKC B RxD3 SDA0 N5 P12 IRQ2 B RxD2 N6 P36 PO14 TIOCA2 N7 P56 TRDATA2 N8 VSS N9 P80 N10 P50 WR0 WR N11 VSS N12 P76 IRQ14 A N13 PH2 N14 PC2 A18 ...

Page 43: ... SCK0 P3 PLLVCC P4 P15 IRQ5 B TCLKB B SCK3 SCL1 P5 P11 IRQ1 B SCK2 P6 P84 P7 P54 TRDATA0 P8 VCC P9 P52 RD P10 PH6 P11 VCC P12 P77 P13 PC6 A22 CS6 D RxD5 P14 PC4 A20 P15 VCC R1 P21 PO1 TIOCA3 TMCI0 RxD0 R2 P17 IRQ7 B TCLKD B TxD3 SCL0 ADTRG1 R3 PLLVSS R4 P13 IRQ3 B TxD2 ADTRG0 R5 P10 IRQ0 B R6 P35 PO13 TIOCA1 TIOCB1 TCLKC A R7 P55 TRDATA1 R8 P82 TRCLK R9 BCLK P53 R10 PH7 R11 PH5 R12 PH3 R13 P75 R14...

Page 44: ...D4 TDI 2 P03 IRQ11 A TMRI3 SCK4 TMS 3 P67 DA1 4 P66 DA0 5 AVSS 6 P02 IRQ10 A TMO2 SCK6 TRST 7 P01 IRQ9 A TMCI2 RxD6 8 P00 IRQ8 A TMRI2 TxD6 9 P65 IRQ15 A 10 EMLE 11 WDTOVF TDO 12 VSS 13 MDE 14 VCL 15 MD1 16 MD0 17 P86 18 P85 19 RES 20 XTAL 21 VSS 22 EXTAL 23 VCC 24 NMI 25 P34 IRQ4 A PO12 TIOCA1 26 P33 IRQ3 A PO11 TIOCC0 TIOCD0 TCLKB A 27 P32 IRQ2 A PO10 TIOCC0 TCLKA A 28 P31 IRQ1 A PO9 TIOCA0 TIOC...

Page 45: ... TIOCC3 TIOCD3 35 P22 PO2 TIOCC3 TMO0 SCK0 36 P21 PO1 TIOCA3 TMCI0 RxD0 37 P20 PO0 TIOCA3 TIOCB3 TMRI0 TxD0 38 P17 IRQ7 B TCLKD B TxD3 SCL0 ADTRG1 39 PLLVCC 40 P16 IRQ6 B TCLKC B RxD3 SDA0 41 PLLVSS 42 P15 IRQ5 B TCLKB B SCK3 SCL1 43 P14 IRQ4 B TCLKA B SDA1 44 P13 IRQ3 B TxD2 ADTRG0 45 P12 IRQ2 B RxD2 46 P11 IRQ1 B SCK2 47 P10 IRQ0 B 48 P37 PO15 TIOCA2 TIOCB2 TCLKD A 49 P36 PO14 TIOCA2 50 P35 PO13...

Page 46: ...7 VSS 58 P82 TRCLK 59 VCC 60 P81 TRSYNC 61 P80 62 BCLK P53 63 P52 RD 64 P51 WR1 BC1 65 P50 WR0 WR 66 P77 67 P76 IRQ14 A 68 P75 69 PC7 A23 CS4 D CS7 D TxD5 70 PC6 A22 CS6 D RxD5 71 PC5 A21 CS5 D SCK5 72 PC4 A20 73 PC3 A19 74 VCC 75 PC2 A18 76 VSS 77 PC1 A17 78 PC0 A16 79 PB7 A15 PO31 TIOCA11 TIOCB11 80 PB6 A14 PO30 TIOCA11 81 PB5 A13 PO29 TIOCA10 TIOCB10 82 PB4 A12 PO28 TIOCA10 83 PB3 A11 PO27 TIOC...

Page 47: ... P74 ADTRG3 87 P73 88 P72 89 P71 CS4 C CS5 C CS6 C CS7 C 90 P70 CS3 B ADTRG2 91 VCC 92 PB0 A8 PO24 TIOCA9 93 VSS 94 PA7 A7 PO23 TIOCA8 TIOCB8 TCLKH 95 PA6 A6 PO22 TIOCA8 96 PA5 A5 PO21 TIOCA7 TIOCB7 TCLKG 97 PA4 A4 PO20 TIOCA7 98 PA3 A3 PO19 TIOCC6 TIOCD6 TCLKF 99 PA2 A2 PO18 TIOCC6 TCLKE 100 PA1 A1 PO17 TIOCA6 TIOCB6 101 PA0 A0 BC0 PO16 TIOCA6 102 PE7 IRQ7 A D15 103 PE6 IRQ6 A D14 104 PE5 IRQ5 A ...

Page 48: ...S4 B 115 P63 CS3 A CS7 A 116 P62 CS2 A CS6 A 117 P61 CS1 CS2 B CS5 A CS6 B CS7 B 118 P60 CS0 CS4 A CS5 B 119 PD3 D3 120 PD2 D2 121 PD1 D1 122 PD0 D0 123 P97 AN15 124 P96 AN14 125 P95 AN13 126 P94 AN12 127 P93 AN11 128 P92 AN10 129 P91 AN9 130 VSS 131 P90 AN8 132 VCC 133 P47 IRQ15 B AN7 134 P46 IRQ14 B AN6 135 P45 IRQ13 B AN5 136 P44 IRQ12 B AN4 137 P43 IRQ11 B AN3 138 P42 IRQ10 B AN2 139 P41 IRQ9 ...

Page 49: ...vels on these pins must not be changed during operation System control RES Input Reset signal input pin This LSI enters the reset state when this signal goes low EMLE Input Input pin to enable on chip emulator signal When the on chip emulator is used this pin should be driven high When not used it should be driven low BSCANP Input Input pin to enable boundary scan signal When this pin is driven hi...

Page 50: ...ress space in byte strobe mode WR Output Strobe signal which indicates that writing to the external address space is in progress in 1 write strobe mode BC0 1 2 Output Strobe signal which indicates that the lower order byte D0 to D7 is valid in access to the external address space in 1 write strobe mode BC1 2 Output Strobe signal which indicates that the higher order byte D8 to D15 is valid in acce...

Page 51: ...ns are used as input capture inputs output compare outputs or PWM outputs TIOCA4 TIOCB4 I O Signals for TGRA4 and TGRB4 These pins are used as input capture inputs output compare outputs or PWM outputs TIOCA5 TIOCB5 I O Signals for TGRA5 and TGRB5 These pins are used as input capture inputs output compare outputs or PWM outputs TIOCA6 TIOCB6 TIOCC6 TIOCD6 I O Signals for TGRA6 to TGRD6 These pins ...

Page 52: ... for the counter overflow signal in watchdog timer mode Serial communication interface TxD0 TxD1 TxD2 TxD3 TxD4 TxD5 TxD6 Output Output pins for data transmission RxD0 RxD1 RxD2 RxD3 RxD4 RxD5 RxD6 Input Input pins for data reception SCK0 SCK1 SCK2 SCK3 SCK4 SCK5 SCK6 I O Input output pins for clock signals I2 C bus interface SCL0 SCL1 I O Input output pins for RIIC clocks Bus can be directly driv...

Page 53: ...6 bit input output pins P10 to P17 I O 8 bit input output pins P20 to P27 I O 8 bit input output pins P30 to P37 I O 8 bit input output pins P40 to P47 I O 8 bit input output pins P50 to P57 I O 8 bit input output pins P53 is an input only pin P60 to P67 I O 8 bit input output pins P70 to P77 I O 8 bit input output pins P80 to P86 I O 7 bit input output pins P90 to P97 I O 8 bit input output pins ...

Page 54: ...e processing is drawn out by memory access subsequent operations may in fact be executed earlier By adopting out of order completion of this kind the execution of instructions is controlled to optimize numbers of clock cycles 2 1 Features High instruction execution rate One instruction in one clock cycle Address space 4 Gbyte linear Register set of the CPU General purpose Sixteen 32 bit registers ...

Page 55: ...er stack pointer USP according to the value of the U bit in the PSW USP User stack pointer ISP Interrupt stack pointer INTB Interrupt table register PC Program counter PSW Processor status word BPC Backup PC BPSW Backup PSW FINTV Fast interrupt vector register FPSW Floating point status word R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 SP General purpose register Control register b31 b0 b...

Page 56: ...pointer SP The stack pointer is switched to operate as the interrupt stack pointer ISP or user stack pointer USP by the value of the stack pointer select bit U in the processor status word PSW 2 2 2 Control Registers This CPU has the following nine control registers Interrupt stack pointer ISP User stack pointer USP Interrupt table register INTB Program counter PC Processor status word PSW Backup ...

Page 57: ... operates as the ISP or USP depends on the value of the stack pointer select bit U in the processor status word PSW Set the ISP or USP to a multiple of four as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation 2 2 2 2 Interrupt Table Register INTB b31 b0 Value after reset Undefined The interrupt table register INTB specifies th...

Page 58: ...flow has occurred 1 An overflow has occurred R W b15 to b4 Reserved The value read is always 0 When writing write 0 to these bits R W b16 I 1 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled R W b17 U 1 Stack Pointer Select 0 Interrupt stack pointer ISP is selected 1 User stack pointer USP is selected R W b19 b18 Reserved The value read is always 0 When writing write 0 to these bits R W b...

Page 59: ...gative O Flag Overflow Flag This flag indicates that an overflow occurred during an operation I Bit Interrupt Enable This bit enables interrupt requests When an exception is accepted the value of this bit becomes 0 U Bit Stack Pointer Select This bit specifies the stack pointer as either the ISP or USP When an exception request is accepted this bit is set to 0 When the processor mode is switched f...

Page 60: ...Value after reset Undefined The backup PSW BPSW is provided to speed up response to interrupts After a fast interrupt has been generated the contents of the processor status word PSW are saved in the BPSW The allocation of bits in the BPSW corresponds to that in the PSW 2 2 2 7 Fast Interrupt Vector Register FINTV b31 b0 Value after reset Undefined The fast interrupt vector register FINTV is provi...

Page 61: ...nderflow has occurred R W 1 b6 CX Inexact Cause Flag 0 No inexact exception has been generated 1 Inexact exception has been generated R W 1 b7 CE Un Implemented Processing Cause Flag 0 No un implemented processing has been encountered 1 Un implemented process has been encountered R W 1 b8 DN 0 Flush Bit of Denormalized Number 0 A denormalized number is handled as a denormalized number 1 A denormal...

Page 62: ...Positive denormalized numbers are treated as 0 negative denormalized numbers as 0 3 When the EV bit is set to 0 the FV flag is enabled 4 When the EO bit is set to 0 the FO flag is enabled 5 When the EZ bit is set to 0 the FZ flag is enabled 6 When the EU bit is set to 0 the FU flag is enabled 7 When the EX bit is set to 0 the FX flag is enabled 8 Once the bit has been set to 1 this value is retain...

Page 63: ...ag Underflow Cause Flag CX Flag Inexact Cause Flag and CE Flag Un Implemented Processing Cause Flag Floating point exceptions include the five specified in the IEEE754 standard namely overflow underflow inexact division by zero and invalid operation For a further floating point exception that is generated upon detection of unimplemented processing the corresponding flag CE is set to 1 The bit that...

Page 64: ...ccumulator ACC b63 Value after reset Undefined b48 b47 b32 b31 b16 b15 b0 Range for reading and writing by MVTACHI and MVFACHI Range for writing by MVTACLO Range for reading by MVFACMI The accumulator ACC is a 64 bit register used for DSP instructions The accumulator is also used for the multiply and multiply and accumulate instructions EMUL EMULU FMUL MUL and RMPA in which case the prior value in...

Page 65: ...NTV 2 3 3 Privileged Instruction Privileged instructions can only be executed in supervisor mode Executing a privileged instruction in user mode produces a privileged instruction exception Privileged instructions include the RTFI RTE and WAIT instructions 2 3 4 Switching Between Processor Modes Manipulating the processor mode select bit PM in the processor status word PSW switches the processor mo...

Page 66: ...bit integer Signed word 16 bit integer Unsigned byte 8 bit integer Signed byte 8 bit integer Legend S Signed bit b31 b0 b31 b0 b15 b0 b15 b0 b7 b0 b7 b0 S S S Figure 2 2 Integer 2 4 2 Floating Point Floating point support is for the single precision floating point type specified in IEEE754 operands of this type can be used in eight floating point operation instructions FADD FCMP FDIV FMUL FSUB FTO...

Page 67: ... the destination register and a bit number in the range from 31 to 0 A bit in memory is specified as the destination address and a bit number from 7 to 0 The addressing modes available to specify addresses are register indirect and register relative Register b31 b0 bit Rn bit 31 to 0 n 0 to 15 b7 b0 bit mem bit 7 to 0 Memory Example Example 30 R1 register R1 bit 30 2 R2 address R2 bit 2 Figure 2 4...

Page 68: ...In the tables LL indicates bits D7 to D0 of the general register LH indicates bits D15 to D8 of the general register HL indicates bits D23 to D16 of the general register and HH indicates bits D31 to D24 of the general register D31 to D24 D23 to D16 D15 to D8 D7 to D0 General purpose register Rm HH HL LH LL Table 2 1 32 Bit Read Operations when Little Endian has been Selected Operation Address of s...

Page 69: ...o address 3 Writing a 32 bit unit to address 4 Address 0 Transfer from LL Address 1 Transfer from LH Transfer from LL Address 2 Transfer from HL Transfer from LH Transfer from LL Address 3 Transfer from HH Transfer from HL Transfer from LH Transfer from LL Address 4 Transfer from HH Transfer from HL Transfer from LH Transfer from LL Address 5 Transfer from HH Transfer from HL Transfer from LH Addr...

Page 70: ... address 2 Reading a 16 bit unit from address 3 Reading a 16 bit unit from address 4 Reading a 16 bit unit from address 5 Reading a 16 bit unit from address 6 Address 0 Transfer to LH Address 1 Transfer to LL Transfer to LH Address 2 Transfer to LL Transfer to LH Address 3 Transfer to LL Transfer to LH Address 4 Transfer to LL Transfer to LH Address 5 Transfer to LL Transfer to LH Address 6 Transf...

Page 71: ...an has been Selected Operation Address of src Reading an 8 bit unit from address 0 Reading an 8 bit unit from address 1 Reading an 8 bit unit from address 2 Reading an 8 bit unit from address 3 Address 0 Transfer to LL Address 1 Transfer to LL Address 2 Transfer to LL Address 3 Transfer to LL Table 2 10 8 Bit Read Operations when Big Endian has been Selected Operation Address of src Reading an 8 b...

Page 72: ...his is regardless of whether the setting on the MDE pin is for little endian or big endian Accordingly changes to the endian do not affect access to I O registers For the arrangements of I O registers refer to the descriptions of registers in the relevant sections 2 5 3 Notes on Access to I O Registers Ensure that access to I O registers is in accord with the following rules For I O registers desi...

Page 73: ...big endian Figure 2 7 shows the arrangement of data in memory 1 bit data Little endian Big endian Address L Address L Byte data Word data Address M Address M 1 Address N Address N 1 Address N 2 Address N 3 Longword data Data image Data type b7 b0 LSB MSB Data image Address 7 6 5 4 3 2 1 0 LSB LSB MSB MSB b7 b0 LSB MSB 7 6 5 4 3 2 1 0 LSB LSB MSB MSB Figure 2 7 Data Arrangement in Memory 2 5 5 Note...

Page 74: ...rivileged instruction exception undefined instruction exception floating point exception non maskable interrupt and reset are allocated to addresses in the range from FFFFFF80h to FFFFFFFFh Figure 2 8 shows the fixed vector table Reserved Reserved FFFFFFDCh FFFFFFFCh FFFFFFE0h FFFFFFE4h FFFFFFE8h FFFFFFECh FFFFFFF0h FFFFFFF4h FFFFFFF8h Reserved Privileged instruction exception Reserved Undefined i...

Page 75: ...or table has a vector number from 0 to 255 Each of the INT instructions which act as the sources of unconditional traps is allocated to the vector that has the same number as that of the instruction itself from 0 to 255 The BRK instruction is allocated to the vector with number 0 Furthermore vector numbers within the set from 0 to 255 may also be allocated to other interrupt sources on a per produ...

Page 76: ... the read processing Data is prefetched from the prefetching start position with three bytes as the upper limit The prefetching start positions of each operation are shown below RMPA instruction The multiplicand address specified by R1 and the multiplier address specified by R2 SCMPU instruction The source address specified by R1 for comparison and the destination address specified by R2 for compa...

Page 77: ... to the register RW can be executed with the register reference by using the bypass process 3 E stage execution stage Operations and address calculations OP are processed in the E stage 4 M stage memory access stage Operand memory accesses OA are processed in the M stage This stage is used only when the memory is accessed and is divided into two sub stages M1 and M2 The RX CPU enables respective m...

Page 78: ...Feb 20 2013 Figure 2 10 shows the pipeline configuration and its operation IF DEC OP OA1 OA2 IF stage BYP RF Pipeline stage Execution processing D stage E stage M1 stage M2 stage One cycle WB stage RW M stage Figure 2 10 Pipeline Configuration and its Operation ...

Page 79: ...Figure 2 11 1 Arithmetic logic instructions division DIV IMM Rd Rs Rd Figure 2 11 3 to 20 1 DIVU IMM Rd Rs Rd Figure 2 11 2 to 18 1 Data transfer instructions register register immediate register MOV MOVU REVL REVW IMM Rd Rs Rd SCCnd Rd STNZ STZ IMM Rd Figure 2 11 1 Transfer instructions load operation MOV MOVU Rs Rd dsp Rs Rd Rs Rd Rs Rd Rs Ri Rb POP Rd Figure 2 12 Throughput 1 Latency 2 2 Transf...

Page 80: ...or Register Register Immediate Register IF D E WB M1 IF D E WB M1 M1 Note When the load operation is executed to the no wait memory the M1 stage is executed in one cycle In other cases the M stage M1 or M2 is executed in multiple cycles 5 stages M2 Figure 2 12 Load Operation IF D E 4 stages M1 IF D E M1 M1 Note The M1 stage is executed until a write request is received during the store operation I...

Page 81: ...s Rd Figure 2 16 2 Arithmetic logic instructions multiply and accumulate operation RMPA B 6 7 floor n 4 4 n 4 n Number of processing bytes 1 RMPA W 6 5 floor n 2 4 n 2 n Number of processing words 1 RMPA L 6 4n n Number of processing longwords 1 Data transfer instructions memory memory transfer MOV Rs Rd dsp Rs Rd Rs dsp Rd dsp Rs Rd PUSH Rs dsp Rs Figure 2 15 3 Bit manipulation instructions memor...

Page 82: ... Rs Rd 3 FDIV IMM Rd Rs Rd 16 FTOI ROUND ITOF Rs Rd 2 Floating point operation instructions memory source operand FADD FSUB Rs Rd dsp Rs Rd 6 FMUL Rs Rd dsp Rs Rd 5 FDIV Rs Rd dsp Rs Rd 18 FTOI ROUND ITOF Rs Rd dsp Rs Rd 4 System manipulation instructions RTE 6 RTFI 3 Notes 1 floor x Max integer that is smaller than x 2 For the number of cycles for throughput and latency see section 2 8 3 Calculat...

Page 83: ...t manipulation store D E M1 M1 Figure 2 15 MOV Instruction Memory Memory Bit Manipulation Instruction Memory Source Operand IF D E EMUL R2 R4 WB D mop1 emul 1 mop2 emul 2 WB Write to R4 Write to R5 E Figure 2 16 EMUL EMULU Instructions Register Register Register Immediate IF D E XCHG R1 R2 D mop1 xchg 1 Read from Write to the register mop2 xchg 2 Write to the register WB E WB Figure 2 17 XCHG Inst...

Page 84: ...e micro operations Legend mop Micro operation stall Pipeline stall 1 Pipeline Flow with Stalls IF D E E E WB IF D stall E WB stall IF stall E WB D stall mop div mop add mop add Figure 2 20 When an Instruction which Requires Multiple Cycles is Executed in the E Stage IF D E M M WB IF D E M WB stall IF D WB E stall M stall stall Other than no wait memory access mop load mop add Figure 2 21 When an I...

Page 85: ... in by the bypass process IF D E ADD R1 R2 SUB R3 R2 WB IF D E WB Bypass process mop add mop sub Figure 2 24 Bypass Process b When WB stages for the memory load and for the operation are overlapped Even when the WB stages for the memory load and for the operation are overlapped the operation processing is pipelined in because the load data and the operation result can be written to the register at...

Page 86: ...g ends out of order completion IF D E MOV R1 R2 IF D E M M M WB WB IF D E WB ADD R4 R5 SUB R6 R7 mop load mop add mop sub Figure 2 27 When Load Data is not Used by the Subsequent Instruction 2 8 3 Calculation of the Instruction Processing Time Though the instruction processing time of the CPU varies according to the pipeline processing the approximate time can be calculated in the following method...

Page 87: ...nterrupt Exception handling routine 4 cycles 6 cycles Times calculated from the values in table 2 15 will be applicable when access to memory from the CPU is always processed with no waiting The on chip RAM and ROM in products of the RX62N RX621 Groups always allows such access Numbers of cycles for response to interrupts can be minimized by placing program code and vectors in on chip ROM and the ...

Page 88: ...0 1 1 0 Boot mode Enabled Disabled 1 0 1 0 User boot mode Enabled Disabled 1 1 1 0 Single chip mode Enabled Disabled Note The on chip ROM is classified into two flash memories ROM and data flash For details see section 26 ROM Flash Memory for Code Storage and section 27 Data Flash Flash Memory for Data Storage Table 3 2 Selection of Operating Modes by Register Setting SYSCR0 Operating Mode On Chip...

Page 89: ...r Register MDMONR Address 0008 0000h b15 b14 b13 b12 b11 b10 b9 b8 Value after reset 1 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 MDE MD1 MD0 x 0 0 Note Depends on the setting of the mode pins MDE MD1 and MD0 x x Bit Symbol Bit Name Description R W b0 MD0 MD0 Status Flag 0 The MD0 pin is 0 1 The MD0 pin is 1 R b1 MD1 MD1 Status Flag 0 The MD1 pin is 0 1 The MD1 pin is 1 R b6 to ...

Page 90: ...ernal Bus Startup Status Flag 0 The external bus is disabled at startup 1 The external bus is enabled at startup R b3 b2 BSW 1 0 External Bus Width Flags 0 0 The 16 bit bus is activated 0 1 Reserved 1 0 The 8 bit bus is activated 1 1 Reserved R b4 BOTS Boot Mode Startup Flag 0 Started with a mode except boot mode 1 Started with boot mode R b5 Reserved This bit is always read as 0 and cannot be mod...

Page 91: ...it On Chip FLASH Enable The ROME bit enables or disables the on chip ROM ROM data flash While this bit is 1 it can be cleared to 0 While this bit is 0 it cannot be set to 1 Once the on chip ROM is disabled by clearing this bit to 0 the on chip ROM can no longer be enabled with the ROME bit A 0 should not be written to this bit during access to the on chip ROM After writing a 0 to this bit to disab...

Page 92: ...0 2013 KEY 7 0 Bits SYSCR0 Key Code The KEY 7 0 bits enable or disable modifying SYSCR0 When writing a value to the ROME or EXBE bit write 5Ah to the KEY 7 0 bits simultaneously If SYSCR0 is modified with a KEY 7 0 value other than 5Ah the ROME and EXBE values remain unchanged ...

Page 93: ...d always be 0 R W SYSCR1 is used to enable or disable the on chip RAM RAME Bit RAM Enable The RAME bit enables or disables the on chip RAM The RAME bit is initialized to 1 after a reset is released A 0 should not be written to this bit during access to the on chip RAM When accessing the on chip RAM immediately after changing the RAME bit from 0 on chip RAM disabled to 1 on chip RAM enabled always ...

Page 94: ...Writing 0 to the EXBE bit causes a transition to single chip mode on chip ROM enabled Writing 0 to the ROME bit causes a transition to on chip ROM disabled extended mode 3 3 3 On Chip ROM Disabled Extended Mode In this mode the on chip ROM is disabled ROME bit 0 in SYSCR0 and the external bus is available as external extended mode EXBE bit 1 in SYSCR0 This mode allows some I O ports to be used as ...

Page 95: ... Mode Pin Setting Figure 3 1 shows operating mode transitions according to the setting of pins MD1 and MD0 Operating modes can shift in the direction of arrow Reset state RES 0 Boot mode User boot mode Single chip mode RES 0 RES 0 RES 0 RES 1 MD1 0 MD0 1 Mode can shift RES 1 MD1 1 MD0 0 RES 1 MD1 1 MD0 1 Figure 3 1 Setting of Pins MD1 and MD0 and Operating Modes ...

Page 96: ...w Single chip mode User boot mode EXBE 0 EXBE 1 EXBE 0 EXBE 1 Mode can shift On chip ROM disabled extended mode On chip ROM Disabled External bus Enabled ROME 0 EXBE 1 On chip ROM Disabled External bus Disabled ROME 0 EXBE 0 On chip ROM enabled extended mode On chip ROM Enabled External bus Enabled ROME 1 EXBE 1 On chip ROM Enabled External bus Disabled ROME 1 EXBE 0 ROME 0 ROME 0 EXBE 0 ROME 0 No...

Page 97: ...ea 1 Reserved area 1 Reserved area 1 Reserved area 1 Reserved area 1 Reserved area 1 Reserved area 1 Notes 1 A reserved area should not be accessed 2 The address space in boot mode and user boot mode is the same as the address space in single chip mode 3 For details on the FCU see section 26 ROM Flash Memory for Code Storage and section 27 Data Flash Flash Memory for Data Storage 0000 0000h 0008 0...

Page 98: ...eral I O registers 0010 8000h On chip ROM data flash 0080 0000h 0100 0000h On chip ROM program ROM write only FFE8 0000h FF7F C000h On chip ROM user boot read only On chip ROM FCU firmware 3 read only FEFF E000h FF00 0000h FCU RAM area 3 Peripheral I O registers 007F 8000h 007F A000h 007F C000h 007F C500h 007F FC00h 0002 0000h 0000 0000h 0008 0000h FFFF FFFFh On chip ROM enabled extended mode 0010...

Page 99: ...ral I O registers 0010 8000h On chip ROM data flash 0080 0000h 0100 0000h On chip ROM program ROM write only FFF0 0000h FF7F C000h On chip ROM user boot read only On chip ROM FCU firmware 3 read only FEFF E000h FF00 0000h FCU RAM area 3 Peripheral I O registers 007F 8000h 007F A000h 007F C000h 007F C500h 007F FC00h 0002 0000h 0000 0000h 0008 0000h FFFF FFFFh On chip ROM enabled extended mode 0010 ...

Page 100: ...eral I O registers 0010 8000h On chip ROM data flash 0080 0000h 0100 0000h On chip ROM program ROM write only FFF4 0000h FF7F C000h On chip ROM user boot read only On chip ROM FCU firmware 3 read only FEFF E000h FF00 0000h FCU RAM area 3 Peripheral I O registers 007F 8000h 007F A000h 007F C000h 007F C500h 007F FC00h 0002 0000h 0000 0000h 0008 0000h FFFF FFFFh On chip ROM enabled extended mode 0010...

Page 101: ...isters 0100 0000h 0800 0000h FF00 0000h Reserved area 0002 0000h Reserved area External address space 0100 0000h 0200 0000h 0300 0000h 0400 0000h 0500 0000h 0600 0000h 0700 0000h CS7 16 Mbytes 01FF FFFFh 02FF FFFFh 03FF FFFFh 04FF FFFFh 05FF FFFFh 06FF FFFFh 07FF FFFFh CS6 16 Mbytes CS5 16 Mbytes CS4 16 Mbytes CS3 16 Mbytes CS2 16 Mbytes CS1 16 Mbytes FFFF FFFFh FFFF FFFFh FF00 0000h CS0 16 Mbytes...

Page 102: ...name field indicates that the entire register is allocated to either the counter or data For the registers of 16 or 32 bits the MSB is listed first 3 Notes on writing to I O registers When writing to an I O register the CPU starts executing the subsequent instruction before completing I O register write This may cause the subsequent instruction to be executed before the post update I O register va...

Page 103: ...f divided cycles for clock synchronization Number of bus cycles for internal peripheral bus 1 or 2 The number of bus cycles of internal peripheral bus 1 or 2 differs according to the register to be accessed For the number of access cycles to each I O register see table 5 1 List of I O Registers When peripheral functions connected to internal peripheral bus 2 or registers for the external bus contr...

Page 104: ...ransfer byte count register DMCBC 32 32 4 to 5 ICLK 0008 201Ch DMAC1 DMA mode register DMMOD 32 32 4 to 5 ICLK 0008 2020h DMAC2 DMA current transfer source address register DMCSA 32 32 4 to 5 ICLK 0008 2024h DMAC2 DMA current transfer destination address register DMCDA 32 32 4 to 5 ICLK 0008 2028h DMAC2 DMA current transfer byte count register DMCBC 32 32 4 to 5 ICLK 0008 202Ch DMAC2 DMA mode regi...

Page 105: ...common DMA interrupt control register DMICNT 8 8 3 ICLK 0008 2517h DMAC common DMA transfer end detect register DMEDET 8 8 3 ICLK 0008 251Bh DMAC common DMA arbitration status register DMASTS 8 8 3 ICLK 0008 3002h BSC CS0 mode register CS0MOD 16 16 1 to 2 BCLK 7 0008 3004h BSC CS0 wait control register 1 CS0WCNT1 32 32 1 to 2 BCLK 7 0008 3008h BSC CS0 wait control register 2 CS0WCNT2 32 32 1 to 2 ...

Page 106: ... 1 to 2 BCLK 7 0008 7010h ICU Interrupt request register 016 IR016 8 8 2 ICLK 0008 7015h ICU Interrupt request register 021 IR021 8 8 2 ICLK 0008 7017h ICU Interrupt request register 023 IR023 8 8 2 ICLK 0008 701Ch ICU Interrupt request register 028 IR028 8 8 2 ICLK 0008 701Dh ICU Interrupt request register 029 IR029 8 8 2 ICLK 0008 701Eh ICU Interrupt request register 030 IR030 8 8 2 ICLK 0008 70...

Page 107: ...upt request register 126 IR126 8 8 2 ICLK 0008 707Fh ICU Interrupt request register 127 IR127 8 8 2 ICLK 0008 7080h ICU Interrupt request register 128 IR128 8 8 2 ICLK 0008 7083h ICU Interrupt request register 131 IR131 8 8 2 ICLK 0008 7084h ICU Interrupt request register 132 IR132 8 8 2 ICLK 0008 7085h ICU Interrupt request register 133 IR133 8 8 2 ICLK 0008 7086h ICU Interrupt request register 1...

Page 108: ...upt request register 184 IR184 8 8 2 ICLK 0008 70B9h ICU Interrupt request register 185 IR185 8 8 2 ICLK 0008 70C6h ICU Interrupt request register 198 IR198 8 8 2 ICLK 0008 70C7h ICU Interrupt request register 199 IR199 8 8 2 ICLK 0008 70C8h ICU Interrupt request register 200 IR200 8 8 2 ICLK 0008 70C9h ICU Interrupt request register 201 IR201 8 8 2 ICLK 0008 70D6h ICU Interrupt request register 2...

Page 109: ...quest destination setting register 066 ISELR066 8 8 2 ICLK 0008 7143h ICU Interrupt request destination setting register 067 ISELR067 8 8 2 ICLK 0008 7144h ICU Interrupt request destination setting register 068 ISELR068 8 8 2 ICLK 0008 7145h ICU Interrupt request destination setting register 069 ISELR069 8 8 2 ICLK 0008 7146h ICU Interrupt request destination setting register 070 ISELR070 8 8 2 IC...

Page 110: ...Interrupt request destination setting register 157 ISELR157 8 8 2 ICLK 0008 719Eh ICU Interrupt request destination setting register 158 ISELR158 8 8 2 ICLK 0008 719Fh ICU Interrupt request destination setting register 159 ISELR159 8 8 2 ICLK 0008 71A1h ICU Interrupt request destination setting register 161 ISELR161 8 8 2 ICLK 0008 71A2h ICU Interrupt request destination setting register 162 ISELR...

Page 111: ...er 0C IER0C 8 8 2 ICLK 0008 720Dh ICU Interrupt request enable register 0D IER0D 8 8 2 ICLK 0008 720Eh ICU Interrupt request enable register 0E IER0E 8 8 2 ICLK 0008 720Fh ICU Interrupt request enable register 0F IER0F 8 8 2 ICLK 0008 7210h ICU Interrupt request enable register 10 IER10 8 8 2 ICLK 0008 7211h ICU Interrupt request enable register 11 IER11 8 8 2 ICLK 0008 7212h ICU Interrupt request...

Page 112: ...upt priority register 47 IPR47 8 8 2 ICLK 0008 734Ch ICU Interrupt priority register 4C IPR4C 8 8 2 ICLK 0008 734Dh ICU Interrupt priority register 4D IPR4D 8 8 2 ICLK 0008 734Eh ICU Interrupt priority register 4E IPR4E 8 8 2 ICLK 0008 734Fh ICU Interrupt priority register 4F IPR4F 8 8 2 ICLK 0008 7350h ICU Interrupt priority register 50 IPR50 8 8 2 ICLK 0008 7351h ICU Interrupt priority register ...

Page 113: ...8E IPR8E 8 8 2 ICLK 0008 738Fh ICU Interrupt priority register 8F IPR8F 8 8 2 ICLK 0008 73F0h ICU Fast interrupt register FIR 16 16 2 ICLK 0008 7400h DTC DTC control register DTCCR 8 8 2 ICLK 0008 7404h DTC DTC vector base register DTCVBR 32 32 2 ICLK 0008 7408h DTC DTC address mode register DTCADMOD 8 8 2 ICLK 0008 740Ch DTC DTC module start register DTCST 8 8 2 ICLK 0008 8000h CMT unit 0 Compare...

Page 114: ... C ADDRC 16 16 2 to 3 PCLK 7 0008 8086h AD2 A D data register D ADDRD 16 16 2 to 3 PCLK 7 0008 8090h AD2 A D control status register ADCSR 8 8 2 to 3 PCLK 7 0008 8091h AD2 A D control register ADCR 8 8 2 to 3 PCLK 7 0008 8092h AD2 ADDRy format select register ADDPR 8 8 2 to 3 PCLK 7 0008 8093h AD2 A D sampling state register ADSSTR 8 8 2 to 3 PCLK 7 0008 80A0h AD3 A D data register A ADDRA 16 16 2...

Page 115: ...ister A TGRA 16 16 2 to 3 PCLK 7 0008 813Ah TPU2 Timer general register B TGRB 16 16 2 to 3 PCLK 7 0008 8140h TPU3 Timer control register TCR 8 8 2 to 3 PCLK 7 0008 8141h TPU3 Timer mode register TMDR 8 8 2 to 3 PCLK 7 0008 8142h TPU3 Timer I O control register H TIORH 8 8 2 to 3 PCLK 7 0008 8143h TPU3 Timer I O control register L TIORL 8 8 2 to 3 PCLK 7 0008 8144h TPU3 Timer interrupt enable regi...

Page 116: ...Timer interrupt enable register TIER 8 8 2 to 3 PCLK 7 0008 8195h TPU7 Timer status register TSR 8 8 2 to 3 PCLK 7 0008 8196h TPU7 Timer counter TCNT 16 16 2 to 3 PCLK 7 0008 8198h TPU7 Timer general register A TGRA 16 16 2 to 3 PCLK 7 0008 819Ah TPU7 Timer general register B TGRB 16 16 2 to 3 PCLK 7 0008 81A0h TPU8 Timer control register TCR 8 8 2 to 3 PCLK 7 0008 81A1h TPU8 Timer mode register T...

Page 117: ...egister L PODRL 8 8 2 to 3 PCLK 7 0008 81Ech 1 PPG0 Next data register H NDRH 8 8 2 to 3 PCLK 7 0008 81EDh 2 PPG0 Next data register L NDRL 8 8 2 to 3 PCLK 7 0008 81EEh 1 PPG0 Next data register H NDRH 8 8 2 to 3 PCLK 7 0008 81EFh 2 PPG0 Next data register L NDRL 8 8 2 to 3 PCLK 7 0008 81F0h PPG1 PPG trigger select register PTRSLR 8 8 2 to 3 PCLK 7 0008 81F6h PPG1 PPG output control register PCR 8...

Page 118: ...ster SSR 6 8 8 2 to 3 PCLK 7 0008 8245h SCI0 Receive data register RDR 8 8 2 to 3 PCLK 7 0008 8246h SCI0 Smart card mode register SCMR 8 8 2 to 3 PCLK 7 0008 8247h SCI0 Serial extended mode register SEMR 8 8 2 to 3 PCLK 7 0008 8248h SCI1 Serial mode register SMR 6 8 8 2 to 3 PCLK 7 0008 8249h SCI1 Bit rate register BRR 8 8 2 to 3 PCLK 7 0008 824Ah SCI1 Serial control register SCR 6 8 8 2 to 3 PCLK...

Page 119: ...ansmit data register TDR 8 8 2 to 3 PCLK 7 0008 8274h SCI6 Serial status register SSR 6 8 8 2 to 3 PCLK 7 0008 8275h SCI6 Receive data register RDR 8 8 2 to 3 PCLK 7 0008 8276h SCI6 Smart card mode register SCMR 8 8 2 to 3 PCLK 7 0008 8277h SCI6 Serial extended mode register SEMR 8 8 2 to 3 PCLK 7 0008 8280h CRC CRC control register CRCCR 8 8 2 to 3 PCLK 7 0008 8281h CRC CRC data input register CR...

Page 120: ...ol for timeout U TMOCNTU 16 16 2 to 3 PCLK 7 0008 832Ch RIIC1 Slave address register L1 SARL1 8 8 2 to 3 PCLK 7 0008 832Dh RIIC1 Slave address register U1 SARU1 8 8 2 to 3 PCLK 7 0008 832Eh RIIC1 Slave address register L2 SARL2 8 8 2 to 3 PCLK 7 0008 832Fh RIIC1 Slave address register U2 SARU2 8 8 2 to 3 PCLK 7 0008 8330h RIIC1 I2C bus bit rate low level register ICBRL 8 8 2 to 3 PCLK 7 0008 8331h...

Page 121: ... Port register PORT 8 8 2 to 3 PCLK 7 0008 C043h P3 Port register PORT 8 8 2 to 3 PCLK 7 0008 C044h P4 Port register PORT 8 8 2 to 3 PCLK 7 0008 C045h P5 Port register PORT 8 8 2 to 3 PCLK 7 0008 C046h P6 Port register PORT 8 8 2 to 3 PCLK 7 0008 C047h P7 Port register PORT 8 8 2 to 3 PCLK 7 0008 C048h P8 Port register PORT 8 8 2 to 3 PCLK 7 0008 C049h P9 Port register PORT 8 8 2 to 3 PCLK 7 0008 ...

Page 122: ...2 to 3 PCLK 7 0008 C105h I O PORT Port function control register 5 PFCR5 8 8 2 to 3 PCLK 7 0008 C106h I O PORT Port function control register 6 PFCR6 8 8 2 to 3 PCLK 7 0008 C107h I O PORT Port function control register 7 PFCR7 8 8 2 to 3 PCLK 7 0008 C108h I O PORT Port function control register 8 PFCR8 8 8 2 to 3 PCLK 7 0008 C109h I O PORT Port function control register 9 PFCR9 8 8 2 to 3 PCLK 7 0...

Page 123: ... 8 8 4 to 5 PCLK 7 0008 C2AFh SYSTEM Deep standby backup register 31 DPSBKR31 8 8 4 to 5 PCLK 7 0008 C300h ICU IRQ detection enable registrar 0 IRQER0 8 8 2 to 3 PCLK 7 0008 C301h ICU IRQ detection enable registrar 1 IRQER1 8 8 2 to 3 PCLK 7 0008 C302h ICU IRQ detection enable registrar 2 IRQER2 8 8 2 to 3 PCLK 7 0008 C303h ICU IRQ detection enable registrar 3 IRQER3 8 8 2 to 3 PCLK 7 0008 C304h I...

Page 124: ...et register FRESETR 16 16 2 to 3 PCLK 7 007F FFBAh FLASH FCU command register FCMDR 16 16 2 to 3 PCLK 7 007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2 to 3 PCLK 7 007F FFCAh FLASH Data flash blank check control register DFLBCCNT 16 16 2 to 3 PCLK 7 007F FFCCh FLASH Flash P E status register FPESTAT 16 16 2 to 3 PCLK 7 007F FFCEh FLASH Data flash blank check status register DFLBCS...

Page 125: ...it 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 SYSTEM MDMONR MDE MD1 MD0 SYSTEM MDSR UBTS BOTS BSW 1 0 EXB IROM SYSTEM SYSCR0 KEY 7 0 EXBE ROME SYSTEM SYSCR1 RAME SYSTEM SBYCR SSBY OPE STS 4 0 SYSTEM MSTPCRA ACSE MSTPA28 MSTPA27 MSTPA23 MSTPA22 MSTPA21 MSTPA20 MSTPA19 MSTPA15 MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA5 MSTPA4 SYSTEM MSTPCRB MSTPB31 MSTPB30 MSTPB29 MSTPB...

Page 126: ...30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 DMAC0 DMMOD OPSEL 3 0 SZSEL 2 0 SMOD 2 0 DMOD 2 0 DMAC1 DMCSA DMAC1 DMCDA DMAC1 DMCBC DMAC1 DMMOD OPSEL 3 0 SZSEL 2 0 SMOD 2 0 DMOD 2 0 DMAC2 DMCSA DMAC2 DMCDA DMAC2 DMCBC DMAC2 DMMOD OPSEL 3 0 SZSEL 2 0 SMOD 2 0 DMOD 2 0 DMAC3 DMCSA DMAC3 DMCDA ...

Page 127: ...ister Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 DMAC3 DMCBC DMAC3 DMMOD OPSEL 3 0 SZSEL 2 0 SMOD 2 0 DMOD 2 0 DMAC0 DMRSA DMAC0 DMRDA DMAC0 DMRBC DMAC1 DMRSA DMAC1 DMRDA DMAC1 DMRBC DMAC2 DMRSA DMAC2 DMRDA DMAC2 DMRBC ...

Page 128: ...3 DMRBC DMAC0 DMCRA DSEL 1 0 BRLOD SRLOD DRLOD DCTG 5 0 DMAC0 DMCRB DSCLR DMAC0 DMCRC ECLR DMAC0 DMCRD DREQ DMAC0 DMCRE DEN DMAC1 DMCRA DSEL 1 0 BRLOD SRLOD DRLOD DCTG 5 0 DMAC1 DMCRB DSCLR DMAC1 DMCRC ECLR DMAC1 DMCRD DREQ DMAC1 DMCRE DEN DMAC2 DMCRA DSEL 1 0 BRLOD SRLOD DRLOD DCTG 5 0 DMAC2 DMCRB DSCLR DMAC2 DMCRC ECLR DMAC2 DMCRD DREQ DMAC2 DMCRE DEN DMAC3 DMCRA DSEL 1 0 BRLOD SRLOD DRLOD DCTG ...

Page 129: ...els DMASTS DASTS0 DASTS1 DASTS2 DASTS3 BSC CS0MOD PRMOD PWENB PRENB EWENB WRMOD BSC CS0WCNT1 CSRWAIT 4 0 CSWWAIT 4 0 CSPRWAIT 2 0 CSPWWAIT 2 0 BSC CS0WCNT2 CSON 2 0 WDON 2 0 WRON 2 0 RDON 2 0 WDOFF 2 0 CSWOFF 2 0 CSROFF 2 0 BSC CS1MOD PRMOD PWENB PRENB EWENB WRMOD BSC CS1WCNT1 CSRWAIT 4 0 CSWWAIT 4 0 CSPRWAIT 2 0 CSPWWAIT 2 0 BSC CS1WCNT2 CSON 2 0 WDON 2 0 WRON 2 0 RDON 2 0 WDOFF 2 0 CSWOFF 2 0 CS...

Page 130: ...WRMOD BSC CS4WCNT1 CSRWAIT 4 0 CSWWAIT 4 0 CSPRWAIT 2 0 CSPWWAIT 2 0 BSC CS4WCNT2 CSON 2 0 WDON 2 0 WRON 2 0 RDON 2 0 WDOFF 2 0 CSWOFF 2 0 CSROFF 2 0 BSC CS5MOD PRMOD PWENB PRENB EWENB WRMOD BSC CS5WCNT1 CSRWAIT 4 0 CSWWAIT 4 0 CSPRWAIT 2 0 CSPWWAIT 2 0 BSC CS5WCNT2 CSON 2 0 WDON 2 0 WRON 2 0 RDON 2 0 WDOFF 2 0 CSWOFF 2 0 CSROFF 2 0 BSC CS6MOD PRMOD PWENB PRENB EWENB WRMOD BSC CS6WCNT1 CSRWAIT 4 0...

Page 131: ...WRCV 3 0 RRCV 3 0 BSC CS1CNT EMODE BSIZE 1 0 EXENB BSC CS1REC WRCV 3 0 RRCV 3 0 BSC CS2CNT EMODE BSIZE 1 0 EXENB BSC CS2REC WRCV 3 0 RRCV 3 0 BSC CS3CNT EMODE BSIZE 1 0 EXENB BSC CS3REC WRCV 3 0 RRCV 3 0 BSC CS4CNT EMODE BSIZE 1 0 EXENB BSC CS4REC WRCV 3 0 RRCV 3 0 BSC CS5CNT EMODE BSIZE 1 0 EXENB BSC CS5REC WRCV 3 0 RRCV 3 0 BSC CS6CNT EMODE BSIZE 1 0 EXENB BSC CS6REC WRCV 3 0 RRCV 3 0 BSC CS7CNT...

Page 132: ...R071 IR ICU IR072 IR ICU IR073 IR ICU IR074 IR ICU IR075 IR ICU IR076 IR ICU IR077 IR ICU IR078 IR ICU IR079 IR ICU IR096 IR ICU IR098 IR ICU IR099 IR ICU IR100 IR ICU IR101 IR ICU IR104 IR ICU IR105 IR ICU IR106 IR ICU IR107 IR ICU IR108 IR ICU IR111 IR ICU IR112 IR ICU IR115 IR ICU IR116 IR ICU IR117 IR ICU IR118 IR ICU IR120 IR ICU IR121 IR ICU IR122 IR ICU IR123 IR ICU IR124 IR ICU IR125 IR IC...

Page 133: ...R145 IR ICU IR146 IR ICU IR149 IR ICU IR150 IR ICU IR151 IR ICU IR152 IR ICU IR154 IR ICU IR155 IR ICU IR156 IR ICU IR157 IR ICU IR158 IR ICU IR159 IR ICU IR160 IR ICU IR161 IR ICU IR162 IR ICU IR165 IR ICU IR166 IR ICU IR167 IR ICU IR168 IR ICU IR170 IR ICU IR171 IR ICU IR174 IR ICU IR175 IR ICU IR176 IR ICU IR177 IR ICU IR178 IR ICU IR179 IR ICU IR180 IR ICU IR181 IR ICU IR182 IR ICU IR183 IR IC...

Page 134: ...26 IR ICU IR227 IR ICU IR228 IR ICU IR229 IR ICU IR230 IR ICU IR231 IR ICU IR232 IR ICU IR233 IR ICU IR234 IR ICU IR235 IR ICU IR236 IR ICU IR237 IR ICU IR238 IR ICU IR239 IR ICU IR240 IR ICU IR241 IR ICU IR246 IR ICU IR247 IR ICU IR248 IR ICU IR249 IR ICU IR250 IR ICU IR251 IR ICU IR252 IR ICU IR253 IR ICU ISELR028 ISEL 1 0 ICU ISELR029 ISEL 1 0 ICU ISELR030 ISEL 1 0 ICU ISELR031 ISEL 1 0 ICU ISE...

Page 135: ...104 ISEL 1 0 ICU ISELR105 ISEL 1 0 ICU ISELR106 ISEL 1 0 ICU ISELR107 ISEL 1 0 ICU ISELR111 ISEL 1 0 ICU ISELR112 ISEL 1 0 ICU ISELR117 ISEL 1 0 ICU ISELR118 ISEL 1 0 ICU ISELR122 ISEL 1 0 ICU ISELR123 ISEL 1 0 ICU ISELR124 ISEL 1 0 ICU ISELR125 ISEL 1 0 ICU ISELR127 ISEL 1 0 ICU ISELR128 ISEL 1 0 ICU ISELR133 ISEL 1 0 ICU ISELR134 ISEL 1 0 ICU ISELR138 ISEL 1 0 ICU ISELR139 ISEL 1 0 ICU ISELR140 ...

Page 136: ... ICU ISELR236 ISEL 1 0 ICU ISELR239 ISEL 1 0 ICU ISELR240 ISEL 1 0 ICU ISELR247 ISEL 1 0 ICU ISELR248 ISEL 1 0 ICU ISELR251 ISEL 1 0 ICU ISELR252 ISEL 1 0 ICU ISELR253 ISEL 1 0 ICU IER02 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IER03 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IER08 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IER09 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IER0C IEN7 IEN6 IEN...

Page 137: ...N4 IEN3 IEN2 IEN1 IEN0 ICU IER1E IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IER1F IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 ICU IPR00 IPR 2 0 ICU IPR01 IPR 2 0 ICU IPR02 IPR 2 0 ICU IPR04 IPR 2 0 ICU IPR05 IPR 2 0 ICU IPR06 IPR 2 0 ICU IPR07 IPR 2 0 ICU IPR20 IPR 2 0 ICU IPR21 IPR 2 0 ICU IPR22 IPR 2 0 ICU IPR23 IPR 2 0 ICU IPR24 IPR 2 0 ICU IPR25 IPR 2 0 ICU IPR26 IPR 2 0 ICU IPR27 IPR 2 0 ICU IPR...

Page 138: ...0 ICU IPR5D IPR 2 0 ICU IPR5E IPR 2 0 ICU IPR5F IPR 2 0 ICU IPR60 IPR 2 0 ICU IPR61 IPR 2 0 ICU IPR62 IPR 2 0 ICU IPR63 IPR 2 0 ICU IPR68 IPR 2 0 ICU IPR69 IPR 2 0 ICU IPR6A IPR 2 0 ICU IPR6B IPR 2 0 ICU IPR70 IPR 2 0 ICU IPR71 IPR 2 0 ICU IPR72 IPR 2 0 ICU IPR73 IPR 2 0 ICU IPR80 IPR 2 0 ICU IPR81 IPR 2 0 ICU IPR82 IPR 2 0 ICU IPR83 IPR 2 0 ICU IPR84 IPR 2 0 ICU IPR85 IPR 2 0 ICU IPR86 IPR 2 0 IC...

Page 139: ...2 Bit 25 17 9 1 Bit 24 16 8 0 DTC DTCADMOD SHORT DTC DTCST DTCST CMT unit 0 CMSTR0 STR1 STR0 CMT0 CMCR CMIE CKS 1 0 CMT0 CMCNT CMT0 CMCOR CMT1 CMCR CMIE CKS 1 0 CMT1 CMCNT CMT1 CMCOR CMT unit 1 CMSTR1 STR3 STR2 CMT2 CMCR CMIE CKS 1 0 CMT2 CMCNT CMT2 CMCOR CMT3 CMCR CMIE CKS 1 0 CMT3 CMCNT CMT3 CMCOR WDT TCSR TMS TME CKS 2 0 WDT WINA WDT TCNT WDT WINB WDT RSTCSR WOVF RSTE AD0 ADDRA AD0 ADDRB AD0 AD...

Page 140: ...GS 2 0 CKS 1 0 MODE 1 0 AD0 ADDPR DPSEL AD0 ADSSTR AD1 ADDRA AD1 ADDRB AD1 ADDRC AD1 ADDRD AD1 ADCSR ADIE ADST CH 3 0 AD1 ADCR TRGS 2 0 CKS 1 0 MODE 1 0 AD1 ADDPR DPSEL AD1 ADSSTR AD2 ADDRA AD2 ADDRB AD2 ADDRC AD2 ADDRD AD2 ADCSR ADIE ADST CH 3 0 AD2 ADCR TRGS 2 0 CKS 1 0 MODE 1 0 AD2 ADDPR DPSEL AD2 ADSSTR AD3 ADDRA AD3 ADDRB AD3 ADDRC AD3 ADDRD AD3 ADCSR ADIE ADST CH 3 0 AD3 ADCR TRGS 2 0 CKS 1 ...

Page 141: ...DR ICSELD ICSELB BFB BFA MD 3 0 TPU0 TIORH IOB 3 0 IOA 3 0 TPU0 TIORL IOD 3 0 IOC 3 0 TPU0 TIER TTGE TCIEV TGIED TGIEC TGIEB TGIEA TPU0 TSR TPU0 TCNT TPU0 TGRA TPU0 TGRB TPU0 TGRC TPU0 TGRD TPU1 TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU1 TMDR ICSELB MD 3 0 TPU1 TIOR IOB 3 0 IOA 3 0 TPU1 TIER TTGE TCIEU TCIEV TGIEB TGIEA TPU1 TSR TCFD TPU1 TCNT TPU1 TGRA TPU1 TGRB TPU2 TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU2 ...

Page 142: ...TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU4 TMDR ICSELB MD 3 0 TPU4 TIOR IOB 3 0 IOA 3 0 TPU4 TIER TTGE TCIEU TCIEV TGIEB TGIEA TPU4 TSR TCFD TPU4 TCNT TPU4 TGRA TPU4 TGRB TPU5 TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU5 TMDR ICSELB MD 3 0 TPU5 TIOR IOB 3 0 IOA 3 0 TPU5 TIER TTGE TCIEU TCIEV TGIEB TGIEA TPU5 TSR TCFD TPU5 TCNT TPU5 TGRA TPU5 TGRB TPU unit 1 TSTRB CST5 CST4 CST3 CST2 CST1 CST0 TPU unit 1 TSYRB SYN...

Page 143: ... 0 TPSC 2 0 TPU7 TMDR ICSELB MD 3 0 TPU7 TIOR IOB 3 0 IOA 3 0 TPU7 TIER TTGE TCIEU TCIEV TGIEB TGIEA TPU7 TSR TCFD TPU7 TCNT TPU7 TGRA TPU7 TGRB TPU8 TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU8 TMDR ICSELB MD 3 0 TPU8 TIOR IOB 3 0 IOA 3 0 TPU8 TIER TTGE TCIEU TCIEV TGIEB TGIEA TPU8 TSR TCFD TPU8 TCNT TPU8 TGRA TPU8 TGRB TPU9 TCR CCLR 2 0 CKEG 1 0 TPSC 2 0 TPU9 TMDR ICSELD ICSELB BFB BFA MD 3 0 TPU9 TIORH ...

Page 144: ...CR G3CMS 1 0 G2CMS 1 0 G1CMS 1 0 G0CMS 1 0 PPG0 PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV PPG0 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 PPG0 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 PPG0 PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PPG0 PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 PPG0 NDRH 1 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 PPG0 NDRL ...

Page 145: ... OSA 1 0 TMR1 TCSR OSB 1 0 OSA 1 0 TMR0 TCORA TMR1 TCORA TMR0 TCORB TMR1 TCORB TMR0 TCNT TMR1 TCNT TMR0 TCCR TMRIS CSS 1 0 CKS 2 0 TMR1 TCCR TMRIS CSS 1 0 CKS 2 0 TMR2 TCR CMIEB CMIEA OVIE CCLR 1 0 TMR3 TCR CMIEB CMIEA OVIE CCLR 1 0 TMR2 TCSR ADTE OSB 1 0 OSA 1 0 TMR3 TCSR OSB 1 0 OSA 1 0 TMR2 TCORA TMR3 TCORA TMR2 TCORB TMR3 TCORB TMR2 TCNT TMR3 TCNT TMR2 TCCR TMRIS CSS 1 0 CKS 2 0 TMR3 TCCR TMRI...

Page 146: ...ND SCI2 RDR SCI2 SCMR BCP2 SDIR SINV SMIF SCI2 SEMR ABCS ACS0 SCI3 SMR 5 CM CHR PE PM STOP CKS 1 0 GM BLK PE PM BCP 1 0 CKS 1 0 SCI3 BRR SCI3 SCR 5 TIE RIE TE RE TEIE CKE 1 0 SCI3 TDR SCI3 SSR 5 TDRE RDRF ORER FER PER TEND TDRE RDRF ORER ERS PER TEND SCI3 RDR SCI3 SCMR BCP2 SDIR SINV SMIF SCI3 SEMR ABCS ACS0 SCI4 SMR 5 CM CHR PE PM STOP CKS 1 0 GM BLK PE PM BCP 1 0 CKS 1 0 SCI4 BRR SCI4 SCR 5 TIE ...

Page 147: ...E IICRST CLO SOWP SCLO SDAO SCLI SDAI RIIC0 ICCR2 BBSY MST TRS SP RS ST RIIC0 ICMR1 MTWP CKS 2 0 BCWP BC 2 0 RIIC0 ICMR2 DLCS SDDL 2 0 TMWE TMOH TMOL TMOS RIIC0 ICMR3 SMBS WAIT RDRFS ACKWP ACKBT ACKBR NF 1 0 RIIC0 ICFER FMPE SCLE NFE NACKE SALE NALE MALE TMOE RIIC0 ICSER HOAE DIDE GCAE SAR2E SAR1E SAR0E RIIC0 ICIER TIE TEIE RIE NAKIE SPIE STIE ALIE TMOIE RIIC0 ICSR1 HOA DID GCA AAS2 AAS1 AAS0 RIIC...

Page 148: ...CNTL RIIC1 SARL1 SVA 7 1 SVA0 RIIC1 SARU1 SVA 9 8 FS RIIC1 SARL2 SVA 7 1 SVA0 RIIC1 SARU2 SVA 9 8 FS RIIC1 ICBRL BRL 4 0 RIIC1 ICBRH BRH 4 0 RIIC1 ICDRT RIIC1 ICDRR P0 DDR B5 B4 B3 B2 B1 B0 P1 DDR B7 B6 B5 B4 B3 B2 B1 B0 P2 DDR B7 B6 B5 B4 B3 B2 B1 B0 P3 DDR B7 B6 B5 B4 B3 B2 B1 B0 P4 DDR B7 B6 B5 B4 B3 B2 B1 B0 P5 DDR B7 B6 B5 B4 B3 B2 B1 B0 P6 DDR B7 B6 B5 B4 B3 B2 B1 B0 P7 DDR B7 B6 B5 B4 B3 B2...

Page 149: ... B2 B1 B0 P3 PORT B7 B6 B5 B4 B3 B2 B1 B0 P4 PORT B7 B6 B5 B4 B3 B2 B1 B0 P5 PORT B7 B6 B5 B4 B3 B2 B1 B0 P6 PORT B7 B6 B5 B4 B3 B2 B1 B0 P7 PORT B7 B6 B5 B4 B3 B2 B1 B0 P8 PORT B6 B5 B4 B3 B2 B1 B0 P9 PORT B7 B6 B5 B4 B3 B2 B1 B0 PA PORT B7 B6 B5 B4 B3 B2 B1 B0 PB PORT B7 B6 B5 B4 B3 B2 B1 B0 PC PORT B7 B6 B5 B4 B3 B2 B1 B0 PD PORT B7 B6 B5 B4 B3 B2 B1 B0 PE PORT B7 B6 B5 B4 B3 B2 B1 B0 PF PORT B...

Page 150: ... DIRQ1E DIRQ0E SYSTEM DPSIFR DNMIF DIRQ3F DIRQ2F DIRQ1F DIRQ0F SYSTEM DPSIEGR DNMIEG DIRQ3EG DIRQ2EG DIRQ1EG DIRQ0EG SYSTEM RSTSR DPSRSTF FLASH FWEPROR FLWE 1 0 SYSTEM DPSBKR0 BKUP07 BKUP06 BKUP05 BKUP04 BKUP03 BKUP02 BKUP01 BKUP00 SYSTEM DPSBKR1 BKUP17 BKUP16 BKUP15 BKUP14 BKUP13 BKUP12 BKUP11 BKUP10 SYSTEM DPSBKR2 BKUP27 BKUP26 BKUP25 BKUP24 BKUP23 BKUP22 BKUP21 BKUP20 SYSTEM DPSBKR3 BKUP37 BKUP...

Page 151: ...UP256 BKUP255 BKUP254 BKUP253 BKUP252 BKUP251 BKUP250 SYSTEM DPSBKR26 BKUP267 BKUP266 BKUP265 BKUP264 BKUP263 BKUP262 BKUP261 BKUP260 SYSTEM DPSBKR27 BKUP277 BKUP276 BKUP275 BKUP274 BKUP273 BKUP272 BKUP271 BKUP270 SYSTEM DPSBKR28 BKUP287 BKUP286 BKUP285 BKUP284 BKUP283 BKUP282 BKUP281 BKUP280 SYSTEM DPSBKR29 BKUP297 BKUP296 BKUP295 BKUP294 BKUP293 BKUP292 BKUP291 BKUP290 SYSTEM DPSBKR30 BKUP307 BK...

Page 152: ...OTR FPKEY 7 0 FPROTCN FLASH FRESETR FRKEY 7 0 FRESET FLASH FCMDR CMDR 7 0 PCMDR 7 0 FLASH FCPSR ESUSPMD FLASH DFLBCCNT BCADR 9 0 BCADR 9 0 BCSIZE FLASH FPESTAT PEERRST 7 0 FLASH DFLBCSTA T BCST FLASH PCKAR PCKA 7 0 Notes 1 When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0 PCR setting the PPG0 NDRH address is 000881ECh When different output triggers are specified...

Page 153: ...output groups 4 and 5 by the PPG1 PCR setting the PPG1 NDRL address is 000881FDh When different output triggers are specified the PPG1 NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh respectively 5 For certain bits functions differ according to whether the mode is serial communications or smart card interface ...

Page 154: ...s of the LSI are initialized by a reset Figure 6 1 shows the targets to be initialized by each reset RSTSR DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR FWEPROR Deep software standby reset Watchdog timer reset Pin reset RES Watchdog timer Internal state other than above and pin states Deep software standby reset generation circuit Register for watchdog timer RSTCSR Registers related to power down function ...

Page 155: ...r down function RSTSR DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR FWEPROR Reset Register for the watchdog timer RSTCSR Reset Reset Registers other than above and internal state Reset Reset Reset Pin states Reset Reset When a reset is released the reset exception handling is started For the reset exception handling see section 9 Exceptions Table 6 3 shows the pin related to reset Table 6 3 Pin Configurati...

Page 156: ... the deep software standby reset is not generated 1 An external interrupt source to cancel the deep software standby reset is generated R W Note Only 0 can be written to this bit RSTSR indicates a source for generating an internal reset DPSRSTF Flag Deep Software Standby Reset Flag The DPSRSTF flag indicates that deep software standby mode is canceled by an external interrupt source specified with...

Page 157: ...lowed in watchdog timer mode R W Note Only 0 can be written to this bit RSTCSR controls the generation of the internal reset signal when TCNT overflows and selects the type of internal reset signal RSTCSR is initialized to 1Fh by a reset signal from the RES pin or a deep software standby reset but not by the WDT internal reset signal caused by a WDT overflow To read this register use 8 bit access ...

Page 158: ...is is an internal reset generated when deep software standby mode is canceled by an interrupt When deep software standby mode is canceled clock oscillation starts and a deep software standby reset is generated at the same time After the time specified with the deep software standby wait time bits WTSTS 5 0 in DPSWCR has passed the deep software standby reset is released For details on the deep sof...

Page 159: ...low to identify a reset generation source No Yes No Yes Deep software standby reset Pin reset Watchdog timer reset RSTCSR RSTE 1 RSTCSR WOVF 1 RSTSR DPSRSTF 1 Reset exception handling Figure 6 2 Example of Flow to Identify a Reset Generation Source 6 5 Usage Notes 6 5 1 Notes on Design of Board The XTAL pin and the reset pin are crossly arranged on the RX610 Group Therefore to avoid the reference ...

Page 160: ...ed to peripheral modules Generates the external bus clock BCLK to be supplied to the external bus Input clock EXTAL frequency 8 to 14 MHz Selection of ICLK PCLK or BCLK The ICLK PCLK or BCLK is selectable independently from EXTAL 8 4 2 and 1 Operating frequency ICLK 8 to 100 MHz PCLK 8 to 50 MHz BCLK 8 to 25 MHz Restrictions for setting clock frequencies ICLK PCLK and ICLK BCLK Connectable resonat...

Page 161: ...sonator The EXTAL pin can also be used to input an external clock For details see section 7 3 2 External Clock Input EXTAL Input BCLK Output This pin is used to supply external devices with the external bus clock BCLK 7 2 Register Descriptions Table 7 3 shows the register of the clock generation circuit Table 7 3 Register of Clock Generation Circuit Register Name Symbol Value after Reset Address A...

Page 162: ... b11 to b8 PCK 3 0 1 Peripheral Module Clock PCLK Select b11 b8 0 0 0 0 8 0 0 0 1 4 0 0 1 0 2 0 0 1 1 1 Settings other than above are prohibited R W b15 to b12 Reserved These bits are always read as 0 The write value should always be 0 R W b19 to b16 BCK 3 0 1 External Bus Clock BCLK Select b19 b16 0 0 0 0 8 0 0 0 1 4 0 0 1 0 2 0 0 1 1 1 Settings other than above are prohibited R W b22 to b20 Rese...

Page 163: ...lect the frequencies of the system clock ICLK peripheral module clock PCLK and external bus clock BCLK PCK 3 0 Bits Peripheral Module Clock PCLK Select These bits select the PCLK frequency The value of these bits indicates a multiplication factor of the input clock EXTAL BCK 3 0 Bits External Bus Clock BCLK Select These bits select the BCLK frequency The value of these bits indicates a multiplicat...

Page 164: ...from the crystal resonator the frequency of the resonator should be in the range of 8 to 14 MHz EXTAL XTAL CL1 CL2 Rd CL1 CL2 10 to 22 pF Figure 7 2 Example of Crystal Resonator Connection Table 7 4 Damping Resistance Reference Values Frequency MHz 8 10 12 14 Rd Ω 200 100 0 0 Figure 7 3 shows an equivalent circuit of the crystal resonator Use a crystal resonator that has the characteristics shown ...

Page 165: ... External clock input Open External clock input XTAL EXTAL a Example of connection with the XTAL pin open b Example of connection with counter phase clock input to the XTAL pin XTAL EXTAL Figure 7 4 Examples of External Clock Input 7 4 PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator by a factor of up to 8 7 5 Frequency Divider The frequency divider divides ...

Page 166: ...d not be set for the ICLK If such a frequency is set the frequency of ICLS will be the same as that of the PCLK or BCLK 7 6 2 Peripheral Module Clock PCLK The peripheral module clock PCLK is the operating clock for peripheral modules The PCLK frequency is specified by the PCK 3 0 bits in SCKCR A frequency higher than the system clock ICLK should not be set for the PCLK If such a frequency is set t...

Page 167: ... Standby Mode is Canceled 2 The relationship among the system clock ICLK peripheral module clock PCLK and external bus clock BCLK is ICLK PCLK and ICLK BCLK and the ICLK has the highest priority For this reason if a setting that does not meet these conditions is made the PCLK and BCLK may have the clock frequency set by the ICK 3 0 bits in SCKCR regardless of the settings of the PCK 3 0 and BCK 3 ...

Page 168: ...ystal resonator place the resonator and its capacitors as close to the XTAL and EXTAL pins as possible Other signal lines should be routed away from the oscillation circuit as shown in figure 7 5 to prevent induction from interfering with correct oscillation The XTAL pin and the reset pin are crossly arranged on the RX610 Group Therefore to avoid the reference from the clock signal the reset signa...

Page 169: ...this LSI enters the normal program execution state but modules except the DTC and DMAC do not operate Table 8 1 Specifications of Low Power Consumption Item Description Multi clock function The frequency division ratio is settable independently for the system clock ICLK peripheral module clock PCLK and external bus clock BCLK BCLK output stop function BCLK output and high output are selectable Mod...

Page 170: ...erating Operating 5 Stopped Retained Stopped Undefined Peripheral modules Operating Stopped 6 Stopped 6 Stopped Undefined I O ports Operating Retained 7 Retained 8 Retained 8 Notes Stopped Retained means that internal register values are retained and internal operations are suspended Stopped Undefined means that internal register values are undefined and power is not supplied to the internal circu...

Page 171: ... bit timer interrupts are enabled when the MSTPA5 or MSTPA4 bit in MSTPCRA is 0 3 NMI and IRQ0 to IRQ15 However IRQ is enabled only when the corresponding bit in SSIER of the ICU is 1 4 NMI and side A of IRQ0 to IRQ3 However NMI and IRQ are enabled only when the corresponding bit in DPSIER is 1 5 If a conflict between a transition to deep software standby mode and generation of software standby mo...

Page 172: ...kup register 4 DPSBKR4 xxh 0008 C294h 8 Deep standby backup register 5 DPSBKR5 xxh 0008 C295h 8 Deep standby backup register 6 DPSBKR6 xxh 0008 C296h 8 Deep standby backup register 7 DPSBKR7 xxh 0008 C297h 8 Deep standby backup register 8 DPSBKR8 xxh 0008 C298h 8 Deep standby backup register 9 DPSBKR9 xxh 0008 C299h 8 Deep standby backup register 10 DPSBKR10 xxh 0008 C29Ah 8 Deep standby backup re...

Page 173: ...alue after Reset Address Access Size Deep standby backup register 29 DPSBKR29 xxh 0008 C2ADh 8 Deep standby backup register 30 DPSBKR30 xxh 0008 C2AEh 8 Deep standby backup register 31 DPSBKR31 xxh 0008 C2AFh 8 Note DPSBKR0 to DPSBKR31 are not initialized and their values are undefined immediately after power on ...

Page 174: ...e 16384 states 0 1 0 1 1 Waiting time 32768 states 0 1 1 0 0 Waiting time 65536 states 0 1 1 0 1 Waiting time 131072 states 0 1 1 1 0 Waiting time 262144 states 0 1 1 1 1 Waiting time 524288 states Settings other than above are prohibited R W b13 Reserved This bit is always read as 0 The write value should always be 0 R W b14 OPE Output Port Enable 0 In software standby mode or deep software stand...

Page 175: ... WR BC0 and BC1 in software standby mode or deep software standby mode or to set the output to the high impedance state SSBY Bit Software Standby The SSBY bit specifies the transition destination after the WAIT instruction is executed When the SSBY bit is set to 0 the LSI enters either sleep mode or all module clock stop mode after execution of the WAIT instruction according to the setting of the ...

Page 176: ... module TMR1 TMR0 0 The module stop state is canceled 1 Transition to the module stop state is made R W b9 to b6 Reserved These bits are always read as 1 The write value should always be 1 R W b10 MSTPA10 Programmable Pulse Generator 1 Unit 1 Module Stop Target module PPG1 0 The module stop state is canceled 1 Transition to the module stop state is made R W b11 MSTPA11 Programmable Pulse Generator...

Page 177: ...le stop state is canceled 1 Transition to the module stop state is made R W b26 to b24 Reserved These bits are always read as 1 The write value should always be 1 R W b27 MSTPA27 Data Transfer Controller Module Stop Target module DTC 0 The module stop state is canceled 1 Transition to the module stop state is made R W b28 MSTPA28 DMA Controller Module Stop Target module DMAC 0 The module stop stat...

Page 178: ... is made R W b21 MSTPB21 I 2 C Bus Interface 0 Unit 0 Module Stop Target module RIIC0 0 The module stop state is canceled 1 Transition to the module stop state is made R W b22 Reserved This bit is always read as 1 The write value should always be 1 R W b23 MSTPB23 CRC Calculator Module Stop Target module CRC 0 The module stop state is canceled 1 Transition to the module stop state is made R W b24 ...

Page 179: ...munication Interface 2 Module Stop Target module SCI2 0 The module stop state is canceled 1 Transition to the module stop state is made R W b30 MSTPB30 Serial Communication Interface 1 Module Stop Target module SCI1 0 The module stop state is canceled 1 Transition to the module stop state is made R W b31 MSTPB31 Serial Communication Interface 0 Module Stop Target module SCI0 0 The module stop stat...

Page 180: ...Bit Name Description R W b0 MSTPC0 RAM0 Module Stop Target module RAM0 0000 0000h to 0000 FFFFh 0 RAM0 run 1 RAM0 stop R W b1 MSTPC1 RAM1 Module Stop Target module RAM1 0001 0000h to 0001 FFFFh 0 RAM1 run 1 RAM1 stop R W b15 to b2 Reserved These bits are always read as 0 The write value should always be 0 R W b31 to b16 Reserved These bits are always read as 1 The write value should always be 1 R ...

Page 181: ...y mode is canceled R W b7 DPSBY Deep Software Standby SSBY b7 0 0 Transition to sleep mode is made after the WAIT instruction is executed 0 1 Transition to sleep mode is made after the WAIT instruction is executed 1 0 Transition to software standby mode is made after the WAIT instruction is executed 1 1 Transition to deep software standby mode is made after the WAIT instruction is executed R W Not...

Page 182: ... Deep Software Standby The DPSBY bit controls transitions to deep software standby mode When the WAIT instruction is executed while the SSBY and DPSBY bits in SBYCR are 1 the LSI enters deep software standby mode through software standby mode This bit is not cleared to 0 when deep software standby mode is canceled by the external interrupt pin Write 0 to this bit to clear When the WDT is used in w...

Page 183: ...W DPSWCR is used to select the time for this LSI to wait until the clock is stabilized when deep software standby mode is canceled by the external interrupt pin DPSWCR is initialized by the reset signal from the RES pin but is not initialized by the internal reset signal that cancels deep software standby mode WTSTS 5 0 Bits Deep Software Standby Waiting Time These bits select the time for this LS...

Page 184: ...ware standby mode by the NMI pin is disabled 1 Canceling deep software standby mode by the NMI pin is enabled R W Note A 1 can be written only once Once 1 is written to the DNMIE bit subsequent write accesses are disabled DPSIER is used to enable or disable the external interrupt pin that cancels deep software standby mode DPSIER is initialized by the reset signal from the RES pin but is not initi...

Page 185: ...r canceling deep software standby mode Each flag is set to 1 when a cancel request specified by the deep standby interrupt edge register DPSIEGR is generated Since each flag is set to 1 when a cancel request is generated in any mode a transition to deep software standby mode should be made after DPSIFR is cleared to 0 Furthermore changing the corresponding P3 ICR or DPSIER setting may lead to a fl...

Page 186: ...ising edge R W b2 DIRQ2EG IRQ2 Edge Select 0 A cancel request is generated at a falling edge 1 A cancel request is generated at a rising edge R W b3 DIRQ3EG IRQ3 Edge Select 0 A cancel request is generated at a falling edge 1 A cancel request is generated at a rising edge R W b6 to b4 Reserved These bits are always read as 0 The write value should always be 0 R W b7 DNMIEG NMI Edge Select 0 A canc...

Page 187: ...andby mode has been canceled by an external interrupt source specified by DPSIER and DPSIEGR and an internal reset has been generated This flag is initialized by the reset signal from the RES pin but is not initialized by the internal reset signal that cancels deep software standby mode Setting condition When deep software standby mode is canceled by an external interrupt source Clearing condition...

Page 188: ...Circuit 8 4 Module Stop Function The module stop function can be set for each on chip peripheral module When the MSTPyj bit y A to C j 0 to 31 in MSTPCRA to MSTPCRC is set to 1 the specified module stops operating and enters the module stop state but the CPU continues to operate independently Clearing the MSTPmi bit to 0 cancels the module stop state allowing the module to restart operating at the...

Page 189: ...that the value written has been reflected 6 Execute the WAIT instruction this automatically sets the PSW I bit 1 of the CPU to 1 Notes 1 For details see section 2 CPU 2 For details see section 10 Interrupt Control Unit ICU 8 5 1 2 Canceling Sleep Mode Sleep mode is canceled by any interrupt reset signal from the RES pin or a reset caused by a watchdog timer overflow Canceling by an interrupt When ...

Page 190: ...or recovery from all module clock stop mode to 1 4 Make either of the following settings for interrupts that are not to be used for recovery from all module clock stop mode Set the priority 4 of interrupts 5 that are not to be used for recovery from all module clock stop mode to a level lower than the setting of the IPL 2 0 bits 3 in PSW of the CPU Set the IENj bit 4 in IERm for the interrupt 5 th...

Page 191: ...es once handling of the given exception is complete However note that in cases where a maskable interrupt has been masked by the CPU the priority level 2 of the interrupt has been set to a value lower than that of the IPL 2 0 bits 3 in PSW of the CPU or a maskable interrupt has been set up as a trigger for transfer by the DTC or DMAC the interrupt will not trigger release from all module clock sto...

Page 192: ...r making the following settings 1 Clear the I bit 1 in PSW of the CPU to 0 2 Set the priority 2 of the interrupt to be used for recovery from software standby mode to a level higher than the setting of the IPL 2 0 bits 1 in PSW 3 Set the IENj bit 2 in IERm for the interrupt to be used for recovery from software standby mode to 1 4 Make either of the following settings for interrupts that are not t...

Page 193: ...et 0 should be written to the status flag the IR bit in IRn of the ICU of the corresponding interrupt at the beginning of the exception handler for the interrupt In addition the interrupt status flag of an interrupt IRQ0 to IRQ15 which is not specified as a trigger for recovery might be set in software standby mode 3 Therefore clear the IR flag after the recovery from software standby mode Notes 1...

Page 194: ... Setting STS4 STS3 STS2 STS1 STS0 Waiting Time States PCLK MHz Unit 50 25 8 0 0 0 0 0 Reserved µs 1 Reserved 1 0 Reserved 1 Reserved 1 0 0 Reserved 1 64 1 3 2 6 8 0 1 0 512 10 25 20 5 64 0 1 1024 20 5 41 0 128 0 1 0 0 0 2048 40 95 81 9 256 0 1 4096 0 08 0 16 0 51 ms 1 0 16384 0 33 0 66 2 05 1 32768 0 655 1 31 4 10 1 0 0 65536 1 31 2 62 8 19 1 131072 2 62 5 24 16 38 1 0 262144 5 25 10 49 32 77 1 52...

Page 195: ... rising edge After that the SSIi bit in SSIER of the ICU and the SSBY bit in SBYCR are set to 1 and then the WAIT instruction is executed Thus a transition to software standby mode is made After that software standby mode is canceled at the rising edge on the IRQ pin To return from the software standby mode settings of the interrupt control unit ICU are also necessary For details see section 10 In...

Page 196: ...r functions stop Furthermore the internal power supply to these modules stops allowing significant reduction in power consumption At this time the contents of all the registers of the CPU and on chip peripheral functions become undefined All the on chip RAM 1 3 data becomes undefined regardless of the setting of the RAMCUT2 to RAMCUT0 bits in DPSBYCR The on chip RAM 0 3 data can be retained by cle...

Page 197: ...pt the DPSRSTF flag in RSTSR is set to 1 2 Canceling by the RES pin When the RES pin is driven low clock oscillation starts and the internal power supply begins at the same time Clocks are supplied to the LSI simultaneously with the start of clock oscillation Be sure to hold the RES pin low until the clock oscillation settles When the RES pin is driven high the CPU begins the reset exception handl...

Page 198: ...Table 8 5 Oscillation Settling Time Setting WTSTS5 WTSTS4 WTSTS3 WTSTS2 WTSTS1 WTSTS0 Waiting Time States EXTAL Input Clock Frequency MHz Unit 12 8 0 0 0 0 0 0 Reserved μs 1 Reserved 1 0 Reserved 1 Reserved 1 0 0 Reserved 1 64 5 3 8 0 1 0 512 42 7 64 0 1 1024 85 3 128 0 1 0 0 0 2048 170 7 256 0 1 4096 0 34 0 51 ms 1 0 16384 1 37 2 05 1 32768 2 73 4 10 1 0 0 65536 5 46 8 19 1 131072 10 92 16 38 1 0...

Page 199: ...YCR and the DPSBY bit in DPSBYCR are set to 1 and then the WAIT instruction is executed Thus a transition to deep software standby mode is made After that deep software standby mode is canceled at the rising edge on the IRQ pin Disabled by an internal reset IRQ exception handling DIRQEG 1 SSBY 1 DPSBY 1 When IOKEEP L When IOKEEP H Oscillator ICLK IRQ IRQ interrupt DIRQnF set request DIRQnEG bit DP...

Page 200: ...t exception handling Program start RSTSR DPSRSTF 0 Set DPSWCR WTSTS5 0 Set oscillation settling ime Read DPSIFR Identify deep software standby mode canceling source 1 Set the following SBYCR SSBY 1 DPSBYCR DPSBY 1 DPSBYCR RAMCUT2 0 Select deep software standby mode Set Pn DDR and Pn DR Set pin states after clearing IOKEEP to 0 Set pin states during and after cancellation of deep software standby m...

Page 201: ...f the bus cycle and goes high When the B3 bit in P5 DDR of P53 is cleared to 0 the BCLK output is disabled and the pin functions as an input port Table 8 6 shows the BCLK pin state in each operating mode Table 8 6 BCLK Pin P53 State in Each Operating Mode Register Settings Normal Operating Mode Sleep Mode All Module Clock Stop Mode Software Standby Mode Deep Software Standby Mode DDR PSTOP1 OPE 0 ...

Page 202: ...d in the DIRQnF flag n 3 to 0 in DPSIFR but are not transferred to the interrupt control unit peripheral modules and I O ports Inputs to the interrupt control unit peripheral modules and I O ports should be controlled by each Pn ICR 8 7 6 Conflict between Transition to Deep Software Standby Mode and Interrupt If a conflict occurs between a transition to deep software standby mode and generation of...

Page 203: ...flow of the program and starting the execution of another flow Such events are called exceptions The RX CPU supports the seven types of exceptions listed in figure 9 1 The occurrence of an exception causes the processor mode to switch to supervisor mode Exceptions Undefined instruction exception Privileged instruction exception Floating point exceptions Reset Non maskable interrupt Interrupts Unco...

Page 204: ... of floating point exceptions is masked when the EX EU EZ EO or EV bit in FPSW is 0 9 1 4 Reset A reset through input of the reset signal to the CPU causes the exception request This has the highest priority of any exception and is always accepted 9 1 5 Non Maskable Interrupt The non maskable interrupt is generated by input of the non maskable interrupt signal to the CPU and is only used when a fa...

Page 205: ...ode when the PM bit in the PSW is 1 Switch to the supervisor mode Hardware pre processing The program is suspended and the exception is accepted Instruction A Instruction B Instruction C Instruction D Instruction C Restarting of the program Processing of user written program code Read the vector Branch to the start of the handling routine Generation of an exception General purpose registers preser...

Page 206: ...s and control registers other than the PC and PSW that are to be used within the exception handling routine must be preserved on the stack by user program code at the start of the exception handling routine On completion of processing by most exception processing handlers registers preserved under program control are restored and the RTE instruction is executed to restore execution from the except...

Page 207: ...ruction that generated the exception Floating point exceptions Instruction canceling type During instruction execution PC value of the instruction that generated the exception Reset Program abandonment type Any machine cycle None Non maskable interrupt During execution of the RMPA SCMPU SMOVB SMOVF SMOVU SSTR SUNTIL and SWHILE instructions Instruction suspending type During instruction execution P...

Page 208: ...nd Site for Saving the Values in the PC and PSW Exception Vector Site for Saving the Values in the PC and PSW Undefined instruction exception Fixed vector table Stack Privileged instruction exception Fixed vector table Stack Floating point exceptions Fixed vector table Stack Reset Fixed vector table Nowhere Non maskable interrupt Fixed vector table Stack Interrupts Fast interrupt FINTV BPC and BPS...

Page 209: ...xception handling routine the user must ensure that these values are saved on the stack b Updating of the PM U and I bits in the PSW I Cleared I Cleared PM Cleared c Saving the values in the PC For the fast interrupt PC BPC For other exceptions PC Stack area d Set the branch destination address of the exception handling routine in the PC Processing is shifted to the exception handling routine by a...

Page 210: ...he stack ISP 2 The processor mode select bit PM the stack pointer select bit U and the interrupt enable bit I in the PSW are cleared to 0 3 The value of the program counter PC is saved on the stack ISP 4 The address of the processing routine is fetched from the vector address FFFFFFD0h 5 The PC is set to the fetched address and processing branches to the start of the exception handling routine 9 5...

Page 211: ...PU SMOVB SMOVF SMOVU SSTR SUNTIL or SWHILE instruction the value of the program counter PC for that instruction is saved For other instructions the PC value of the next instruction is saved Saving of the PC is in the backup PC BPC for fast interrupts 4 The processor interrupt priority level bits IPL 2 0 in the PSW indicate the interrupt priority level of the interrupt 5 The address of the processi...

Page 212: ...urn Undefined instruction exception RTE Privileged instruction exception RTE Floating point exceptions RTE Reset Return is impossible Non maskable interrupt Return is impossible Interrupts Fast interrupt RTFI Other than the above RTE Unconditional trap RTE 9 7 Order of Priority for Exceptions The order of priority for exceptions is given in table 9 4 When multiple exceptions are generated at the s...

Page 213: ...ling edges One of these detection methods can be set for each source Non maskable interrupt NMI pin interrupts Interrupts from the NMI pin Number of sources 1 Interrupt detection Falling edge rising edge Interrupt priority Specified by registers Vector address Since a vector address is allocated to each interrupt source interrupt sources need not be identified by the software program Fast interrup...

Page 214: ...r DTC to CPU switching IR clear DMAC to CPU switching Legend NMICR NMIER NMICLR NMISR IRQER IRQCR SSIER NMI pin interrupt control register Non maskable interrupt enable register Non maskable interrupt clear register Non maskable interrupt status register Interrupt detection enable register IRQ control register Software standby release IRQ enable register IR IER ISELR FIR IPR Interrupt request regi...

Page 215: ...upt request register 073 IR073 00h 0008 7049h 8 Interrupt request register 074 IR074 00h 0008 704Ah 8 Interrupt request register 075 IR075 00h 0008 704Bh 8 Interrupt request register 076 IR076 00h 0008 704Ch 8 Interrupt request register 077 IR077 00h 0008 704Dh 8 Interrupt request register 078 IR078 00h 0008 704Eh 8 Interrupt request register 079 IR079 00h 0008 704Fh 8 Interrupt request register 0...

Page 216: ...ster 149 IR149 00h 0008 7095h 8 Interrupt request register 150 IR150 00h 0008 7096h 8 Interrupt request register 151 IR151 00h 0008 7097h 8 Interrupt request register 152 IR152 00h 0008 7098h 8 Interrupt request register 154 IR154 00h 0008 709Ah 8 Interrupt request register 155 IR155 00h 0008 709Bh 8 Interrupt request register 156 IR156 00h 0008 709Ch 8 Interrupt request register 157 IR157 00h 000...

Page 217: ...terrupt request register 227 IR227 00h 0008 70E3h 8 Interrupt request register 228 IR228 00h 0008 70E4h 8 Interrupt request register 229 IR229 00h 0008 70E5h 8 Interrupt request register 230 IR230 00h 0008 70E6h 8 Interrupt request register 231 IR231 00h 0008 70E7h 8 Interrupt request register 232 IR232 00h 0008 70E8h 8 Interrupt request register 233 IR233 00h 0008 70E9h 8 Interrupt request regist...

Page 218: ...tion setting register 104 ISELR104 00h 0008 7168h 8 Interrupt request destination setting register 105 ISELR105 00h 0008 7169h 8 Interrupt request destination setting register 106 ISELR106 00h 0008 716Ah 8 Interrupt request destination setting register 107 ISELR107 00h 0008 716Bh 8 Interrupt request destination setting register 111 ISELR111 00h 0008 716Fh 8 Interrupt request destination setting re...

Page 219: ... request destination setting register 219 ISELR219 00h 0008 71DBh 8 Interrupt request destination setting register 220 ISELR220 00h 0008 71DCh 8 Interrupt request destination setting register 223 ISELR223 00h 0008 71DFh 8 Interrupt request destination setting register 224 ISELR224 00h 0008 71E0h 8 Interrupt request destination setting register 227 ISELR227 00h 0008 71E3h 8 Interrupt request destin...

Page 220: ...00h 0008 7307h 8 Interrupt priority register 20 IPR20 00h 0008 7320h 8 Interrupt priority register 21 IPR21 00h 0008 7321h 8 Interrupt priority register 22 IPR22 00h 0008 7322h 8 Interrupt priority register 23 IPR23 00h 0008 7323h 8 Interrupt priority register 24 IPR24 00h 0008 7324h 8 Interrupt priority register 25 IPR25 00h 0008 7325h 8 Interrupt priority register 26 IPR26 00h 0008 7326h 8 Inter...

Page 221: ...ter 6A IPR6A 00h 0008 736Ah 8 Interrupt priority register 6B IPR6B 00h 0008 736Bh 8 Interrupt priority register 70 IPR70 00h 0008 7370h 8 Interrupt priority register 71 IPR71 00h 0008 7371h 8 Interrupt priority register 72 IPR72 00h 0008 7372h 8 Interrupt priority register 73 IPR73 00h 0008 7373h 8 Interrupt priority register 80 IPR80 00h 0008 7380h 8 Interrupt priority register 81 IPR81 00h 0008 ...

Page 222: ... register 1 IRQCR1 00h 0008 C321h 8 IRQ control register 2 IRQCR2 00h 0008 C322h 8 IRQ control register 3 IRQCR3 00h 0008 C323h 8 IRQ control register 4 IRQCR4 00h 0008 C324h 8 IRQ control register 5 IRQCR5 00h 0008 C325h 8 IRQ control register 6 IRQCR6 00h 0008 C326h 8 IRQ control register 7 IRQCR7 00h 0008 C327h 8 IRQ control register 8 IRQCR8 00h 0008 C328h 8 IRQ control register 9 IRQCR9 00h 0...

Page 223: ...nterrupt request If the flag is set to 1 while interrupt requests are enabled by the IENj bit in IERi an interrupt request signal is output to the destination that has been specified by the ISEL 1 0 bits in ISELRi When an interrupt request from the source is detected in the source of interrupt generation the flag is set to 1 For the actual interrupt to be generated the interrupt enable bit of the ...

Page 224: ... setting of the ISEL 1 0 bits in ISELRi is 01b and the setting of the DISEL bit in MRB of the DTC is 0 activation of the DTC If the setting of the ISEL 1 0 bits in ISELRi is 10b activation of the DMAC Level detection IRQMD 1 0 bits in IRQCRn 00b Setting condition Generation of the interrupt signal from the source Clearing conditions Writing of 0 with the IRQn pin at the high level 1 2 Disabling th...

Page 225: ...not be selected as an interrupt request destination for some interrupt sources In such cases the lowest 1 bit is valid and the upper 7 bits are reserved The reserved bits are read as 0 The write value to the reserved bits should always be 0 The ISELRi register is used to set the destination of an interrupt request ISEL 1 0 Bits Interrupt Destination These bits specify the destination of an interru...

Page 226: ...bit is read as 0 The IERm register is used to enable or disable an interrupt request to the CPU and DMAC DTC activation request IENj Bits Interrupt Request Enable j 0 to 7 There is an interrupt request enable bit for each interrupt source For the correspondence between interrupt sources and interrupt request enable bits see table 10 4 Interrupt Vector Table When an IENj bit is 1 the corresponding ...

Page 227: ...F in hexadecimal notation For the correspondence between interrupt sources and groups see table 10 4 Interrupt Vector Table IPR 2 0 Bits Interrupt Priority Level Select These bits specify the priority level of interrupt requests Priority levels specified by the IPR 2 0 bits are used only to determine the priority of interrupt requests to the CPU and do not affect activation requests to the DTC and...

Page 228: ... Interrupt Vector Number The FVCT 7 0 bits specify the vector number of a source for use as the fast interrupt When the CPU is the interrupt request destination and an interrupt request corresponding to the vector number specified with the FVCT 7 0 bits is generated while the FIEN bit is 1 the interrupt request is output to the CPU as the fast interrupt regardless of the setting of the IPRi regist...

Page 229: ...l interrupt source is disabled 1 Detection of the signal on the corresponding IRQn pin as an external interrupt source is enabled n 0 to 15 R W b7 to b1 Reserved These bits are read as 0 The write value should always be 0 R W The IRQERn register is used to enable or disable the detection of the corresponding external interrupt source interrupt on the corresponding IRQn pin n 0 to 15 IRQEN Bit IRQ ...

Page 230: ...read as 0 The write value should always be 0 R W The IRQCRn register is used to set up the external interrupt IRQn pin n 0 to 15 The contents of this register should be modified while the corresponding interrupt request enable bit is set to disable an interrupt request IERm IENj bit is 0 After modification of the contents of this register the IR flag should be cleared and then the interrupt reques...

Page 231: ...bled R W b7 to b1 Reserved These bits are read as 0 The write value should always be 0 R W Note A 1 can be written to this bit only once and subsequent write accesses are no longer enabled The NMIER register is used to enable the non maskable interrupt NMIEN Bit NMI Enable This bit enables interrupts by the signal on the NMI pin A 1 can be written to this bit only once Once the interrupt has been ...

Page 232: ...Reserved These bits are read as 0 The write value should always be 0 R W b3 NMIMD NMI Detection Select 0 Falling edge 1 Rising edge R W b7 to b4 Reserved These bits are read as 0 The write value should always be 0 R W The NMICR register is used to set up the NMI interrupt on the NMI pin Change the setting before enabling the NMI setting the NMIEN bit in NMIER to 1 NMIMD Bit NMI Detection Sense Sel...

Page 233: ...egister is used to monitor the non maskable interrupt status To clear the NMISR NMIST flag to 0 set the NMICLR NMICLR bit to 1 After that confirm that the NMISR NMIST flag is 0 and then execute the next instruction NMIST Flag NMI Status Flag The NMIST flag indicates the NMI pin interrupt request This is a read only flag and is cleared by the NMICR bit in NMICLR Setting condition This flag is set t...

Page 234: ...s bit is always read as 0 Writing 1 to this bit clears the NMIST flag in NMISR Writing 0 to this bit has no effect R W b7 to b1 Reserved These bits are read as 0 The write value should always be 0 R W Note Only 1 can be written to this bit The NMICLR register is used to clear the non maskable interrupt status register NMISR NMICLR Bit NMI Clear Writing 1 to this bit clears the NMIST flag in NMISR ...

Page 235: ...ated in the software standby state the interrupt control unit returns from the software standby state after the oscillation settling time n 0 to 15 R W b1 SSI1 R W b2 SSI2 R W b3 SSI3 R W b4 SSI4 R W b5 SSI5 R W b6 SSI6 R W b7 SSI7 R W b8 SSI8 R W b9 SSI9 R W b10 SSI10 R W b11 SSI11 R W b12 SSI12 R W b13 SSI13 R W b14 SSI14 R W b15 SSI15 R W The SSIER register is used to set whether to use the IRQ...

Page 236: ...y from all module clock stop mode Table 10 4 Interrupt Vector Table Priority Interrupt Request Source Name Vector Number Vector Address Offset Form of Detection Selectable Interrupt Request Destination IER IPR CPU DTC DMAC Sstb Recovery Sacs Recovery High Low Reserved 0 0000h Reserved 1 0004h Reserved 2 0008h Reserved 3 000Ch Reserved 4 0010h Reserved 5 0014h Reserved 6 0018h Reserved 7 001Ch Rese...

Page 237: ... 0134h Edge Level ER09 IEN5 IPR2D IRQ14 78 0138h Edge Level ER09 IEN6 IPR2E IRQ15 79 013Ch Edge Level ER09 IEN7 IPR2F Reserved 80 to 95 0140h to 017Ch WDT WOVI 96 0180h Edge ER0C IEN0 IPR40 Reserved 97 0184h ER0C IEN1 AD0 ADI0 98 0188h Edge ER0C IEN2 IPR44 AD1 ADI1 99 018Ch Edge ER0C IEN3 IPR45 AD2 ADI2 100 0190h Edge ER0C IEN4 IPR46 AD3 ADI3 101 0194h Edge ER0C IEN5 IPR47 Reserved 102 0198h ER0C ...

Page 238: ...h Edge ER11 IEN1 TPU6 TGI6A 138 0228h Edge ER11 IEN2 IPR58 TGI6B 139 022Ch Edge ER11 IEN3 TGI6C 140 0230h Edge ER11 IEN4 TGI6D 141 0234h Edge ER11 IEN5 TCI6V 142 0238h Edge ER11 IEN6 IPR59 Reserved 143 023Ch ER11 IEN7 Reserved 144 0240h ER12 IEN0 TPU7 TGI7A 145 0244h Edge ER12 IEN1 IPR5A TGI7B 146 0248h Edge ER12 IEN2 Reserved 147 024Ch ER12 IEN3 Reserved 148 0250h ER12 IEN4 TCI7V 149 0254h Edge E...

Page 239: ...179 02CCh Edge IER16 EN3 TMR2 CMIA2 180 02D0h Edge IER16 EN4 IPR6A CMIB2 181 02D4h Edge IER16 EN5 OVI2 182 02D8h Edge IER16 EN6 TMR3 CMIA3 183 02DCh Edge IER16 EN7 IPR6B CMIB3 184 02E0h Edge IER17 EN0 OVI3 185 02E4h Edge IER17 EN1 Reserved 186 02E8h IER17 EN2 Reserved 187 02ECh IER17 EN3 Reserved 188 02F0h IER17 EN4 Reserved 189 02F4h IER17 EN5 Reserved 190 02F8h IER17 EN6 Reserved 191 02FCh IER17...

Page 240: ...ER1B IEN3 TXI1 220 0370h Edge IER1B IEN4 TEI1 221 0374h Level IER1B IEN5 SCI2 ERI2 222 0378h Level IER1B IEN6 IPR82 RXI2 223 037Ch Edge IER1B IEN7 TXI2 224 0380h Edge IER1C IEN0 TEI2 225 0384h Level IER1C IEN1 SCI3 ERI3 226 0388h Level IER1C IEN2 IPR83 RXI3 227 038Ch Edge IER1C IEN3 TXI3 228 0390h Edge IER1C IEN4 TEI3 229 0394h Level IER1C IEN5 SCI4 ERI4 230 0398h Level IER1C IEN6 IPR84 RXI4 231 0...

Page 241: ...9 03E4h Level IER1F IEN1 PR8B RIIC1 ICEEI1 250 03E8h Level IER1F IEN2 PR8C ICRXI1 251 03ECh Edge IER1F IEN3 PR8D ICTXI1 252 03F0h Edge IER1F IEN4 PR8E ICTEI1 253 03F4h Level IER1F IEN5 PR8F Reserved 254 03F8h IER1F IEN6 Reserved 255 03FCh IER1F IEN7 Legend Selectable Not selectable 10 3 2 Fast Interrupt Vector Address The vector address for the interrupt that corresponds to the vector number setti...

Page 242: ...bling and Disabling Interrupts The following settings are required to enable an interrupt requests In the case of interrupt requests from peripheral modules enabling of interrupt output for the corresponding source by the setting of the interrupt enable bit or bits of the peripheral module In the case of external interrupts enabling of interrupt output in response to signals on the corresponding I...

Page 243: ...the selected destination immediately after the point of transition of the interrupt signal If the destination accepts the interrupt request the IR flag in IRi is automatically cleared to 0 Therefore the software being executed does not have to clear the IR flag Interrupt signal IR flag in IRi Acceptance of interrupt request by destination Figure 10 2 Operation of the IR Flag in IRi in the Case of ...

Page 244: ...n Operation is individually described for the cases of level detection of peripheral module interrupts and external interrupts Figure 10 5 shows how the IR flag in IRi operates in the case of level detection of an interrupt from a peripheral function When the IR flag in IRi for an interrupt from a peripheral module has been set to 1 this setting is maintained while generation of the interrupt sign...

Page 245: ...for the high level on the IRQn pin Interrupt signal IRQn detects low level IR flag in IRi After acceptance of the interrupt the signal on the IRQn pin is set to the high level 0 is written to the IR flag in IRi CPU Interrupt handling Figure 10 6 Operation of the IR Flag in IRi in the Case of Level Detection of an External Interrupt Once the IR flag in IRi has been set to 1 if the interrupt is disa...

Page 246: ...ansfers The value of the ISEL 1 0 bits in ISELRi is kept at 01b until the transfer counter reaches 0 On completion of data transfer i e when the transfer counter reaches 0 the ISEL 1 0 bits are automatically updated to 00b At this point the interrupt control unit conveys the interrupt request to the CPU When the DISEL bit in MRB of the DTC is set to 1 the ISEL 1 0 bits in ISELRi are automatically ...

Page 247: ...selected form of DMA transfer is single operand transfer or nonstop transfer modify the value of the bits within the corresponding interrupt exception handler When the selected form of DMA transfer is consecutive operand transfer modify the value of the bits on completion of all DMA transfer on activated channels 1 When the same interrupt source is activating multiple channels regardless of the ty...

Page 248: ...ermining Priority when the DTC is the Destination of the Interrupt Request The IPR 2 0 bits in IPRi have no effect on a group for which 01b is set in the ISEL 1 0 bits in ISELRi An interrupt source with a smaller vector number takes precedence 3 Determining Priority when the DMAC is the Destination of the Interrupt Request For a group for which 10b or 11b is set in the ISEL 1 0 bits in ISELRi the ...

Page 249: ...ion and requesting of the external interrupt 2 Set the IRQMD 1 0 bits in IRQCRn 3 Clear the IR flag in IRi 4 Use the IRQEN bit in IRQERn and IENj bit in IERi to enable detection and requesting of the external interrupt For details on operation in the cases of edge and level detected external interrupts see section 10 4 2 Interrupt Status Flag When an external interrupt is in use the input buffer o...

Page 250: ...e NMICLR bit in NMICLR Then before executing the next instruction confirm that the NMIST flag in NMISR has been cleared To prevent malfunctions in systems that do not require interrupts via the NMI pin the NMI is disabled by default If a system is to use the NMI the procedure below must be included at the beginning of processing by all programs Procedure for Using the NMI 1 Set the stack pointer S...

Page 251: ...nit Clock Sleep All interrupts including NMI pin interrupts Runs All module clock stop Peripheral function interrupts WDT TMR external interrupts NMI pin interrupts Runs Software standby External interrupts NMI pin interrupts Stopped Note For details see section 8 Low Power Consumption 10 6 1 Returning from Sleep Mode and All Module Clock Stop Mode The interrupt control unit can return operation f...

Page 252: ...n specified as the fast interrupt is the highest priority interrupt other than the NMI regardless of the setting of the IPR 2 0 bits in IPRi However if the interrupt source specified as the fast interrupt is to be used as a trigger for return from software standby mode the setting of the IPR 2 0 bits in IPRi for that interrupt source must satisfy the above relevant condition above To cancel softwa...

Page 253: ...e to check that the NMISR NMIST flag is 0 before executing the WAIT instruction 10 7 3 Notes on Transferring DMAC DTC Using Communication Function SCI RIIC When the DMAC DTC is activated using an interrupt from the communication function the DMAC DTC cannot accept an activation request from the communication function and may not perform DMAC DTC transfer In this phenomenon when the next transfer r...

Page 254: ...upt DISEL 0 Impossible 6 CPU interrupt DISEL 1 Possible Note 1 Communication interrupts include transmit data empty and receive data full interrupts from SCI and RIIC Note 2 In the final transfer if the DTC is re set too late for the transfer request of the next packet to be transmitted received the same problem may occur as with the case in DESEL 1 When the DMAC is used with ISEL 1 0 11b use the ...

Page 255: ... 1 Set IRi IR to 1 Yes No Multiple interrupt disabled Set PSW I to 1 2 Communication Function SCI RIIC Receive Buffer Full Flag SSR RDRF 1 ICSR2 RDRF 1 Transmit Buffer Empty Flag SSR TDRE 1 ICSR2 TDRE 1 Note 1 Determination of internal source in communication Note 2 This step is not required when multiple interrupt is not used Figure 10 10 Flowchart for Measures with DISEL 1 ...

Page 256: ...OM Operates in synchronization with the system clock ICLK Internal peripheral bus Internal peripheral bus 1 Connected to peripheral modules Operates in synchronization with the system clock ICLK Internal peripheral bus 2 Connected to peripheral modules on chip ROM for programming and erasure and data flash memory Operates in synchronization with the peripheral module clock PCLK External bus Connec...

Page 257: ... ROM and on chip RAM or to on chip ROM and external address space is possible 11 2 2 Internal Main Buses The internal main buses consist of a bus for use by the CPU internal main bus 1 and a bus for use by the other bus master modules i e the DMAC and DTC internal main bus 2 Requests for bus mastership from the DMAC and DTC are arbitrated by internal main bus 2 The order of priority is DMAC and th...

Page 258: ...r management Chip select signals can be output for each area An 8 bit bus space or a 16 bit bus space is selectable for each area An endian mode can be specified for each area Wait control function Recovery cycles can be inserted Read recovery Up to 15 cycles Write recovery Up to 15 cycles Cycle wait function Wait for up to 31 cycles page access up to 7 cycles Wait control can be used to set up th...

Page 259: ...5 is selected CS6 Output A strobe signal indicating that area 6 CS6 is selected CS7 Output A strobe signal indicating that area 7 CS7 is selected RD Output A strobe signal indicating that reading from an external address space is in progress WR0 Output A strobe signal the WR0 signal being at the low level during writing to an external address space in byte strobe mode indicates that the higher ord...

Page 260: ...example of parallel operations is given in figure 11 2 In this example the CPU is able to employ the instruction and operand buses for simultaneous access to on chip ROM and on chip RAM respectively Furthermore the DMAC simultaneously employs internal main bus 2 for access to a peripheral bus or the external bus during access to on chip RAM and ROM by the CPU CPU operand access RAM ROM CPU instruc...

Page 261: ...ycle register CS6REC 0000h 0008 386Ah 16 CS7 control register CS7CNT 0000h 0008 3872h 16 CS7 recovery cycle register CS7REC 0000h 0008 387Ah 16 CS0 mode register CS0MOD 0000h 0008 3002h 16 CS0 wait control register 1 CS0WCNT1 0707 0707h 0008 3004h 32 CS0 wait control register 2 CS0WCNT2 0000 0007h 0008 3008h 32 CS1 mode register CS1MOD 0000h 0008 3012h 16 CS1 wait control register 1 CS1WCNT1 0707 ...

Page 262: ...707h 0008 3064h 32 CS6 wait control register 2 CS6WCNT2 0000 0007h 0008 3068h 32 CS7 mode register CS7MOD 0000h 0008 3072h 16 CS7 wait control register 1 CS7WCNT1 0707 0707h 0008 3074h 32 CS7 wait control register 2 CS7WCNT2 0000 0007h 0008 3078h 32 Bus error source clear register BERCLR 00h 0008 1300h 8 Bus error monitoring enable register BEREN 00h 0008 1304h 8 Bus error interrupt enable registe...

Page 263: ... endian of operating mode 1 Endian of area i i 0 to 7 is not the endian of operating mode R W b15 to b9 Reserved These bits are always read as 0 The write value should always be 0 R W Notes 1 After a reset the value of the EXENB bit in CS0CNT is 1 and the value of the EXENB bit in CSiCNT i 1 to 7 is 0 2 The value of the BSIZE 1 0 bits in CS0CNT after a reset is 10 CSiCNT is used to set enabling di...

Page 264: ...ecifies the endian of each area When the endian setting for each area is different from that for the chip no instruction code can be allocated in the area If the instruction code is allocated to the external address space it must be allocated to areas where the endian setting is the same as that for the chip ...

Page 265: ... 1 1 1 0 Fourteen recovery cycles are inserted 1 1 1 1 Fifteen recovery cycles are inserted R W b7 to b4 Reserved These bits are always read as 0 The write value should always be 0 R W b11 to b8 WRCV 3 0 Write Recovery b11 b8 0 0 0 0 No recovery cycle is inserted 0 0 0 1 One recovery cycle is inserted 0 0 1 0 Two recovery cycles are inserted 0 0 1 1 Three recovery cycles are inserted 0 1 0 0 Four ...

Page 266: ...hese bits one to 15 recovery cycles are inserted in the following cases When a read access is made to the external bus after a write access to the external bus Recovery cycles are also inserted when consecutive accesses are made in the same area No recovery cycle is inserted during a write access after a write access Table 11 7 Insertion of Recovery Cycles Access Type External Address Space Insert...

Page 267: ...d R W b14 to b10 Reserved These bits are always read as 0 The write value should always be 0 R W b15 PRMOD Page Read Access Mode Select 0 Normal access compatible mode 1 External data read continuous assertion mode R W CSiMOD is used to set access modes of each area in the external address space WRMOD Bit Write Access Mode Select This bit selects a write access operating mode Writing 0 to this bit...

Page 268: ...isables page read accesses PWENB Bit Page Write Access Enable This bit enables or disables page write accesses PRMOD Bit Page Read Access Mode Select This bit selects a page read access operating mode Writing 0 to this bit selects normal access compatible mode where the RD signal is negated and RD assert wait is inserted each time a piece of data is read However when there is no RD assert wait the...

Page 269: ... cycles is inserted 1 0 0 Wait with a length of 4 clock cycles is inserted 1 0 1 Wait with a length of 5 clock cycles is inserted 1 1 0 Wait with a length of 6 clock cycles is inserted 1 1 1 Wait with a length of 7 clock cycles is inserted R W b7 to b3 Reserved These bits are always read as 0 The write value should always be 0 R W b10 to b8 CSPRWAIT 2 0 Page Read Cycle Wait Select 2 b10 b8 0 0 0 N...

Page 270: ...0 1 1 1 0 Wait with a length of 14 clock cycles is inserted 0 1 1 1 1 Wait with a length of 15 clock cycles is inserted 1 0 0 0 0 Wait with a length of 16 clock cycles is inserted 1 0 0 0 1 Wait with a length of 17 clock cycles is inserted 1 0 0 1 0 Wait with a length of 18 clock cycles is inserted 1 0 0 1 1 Wait with a length of 19 clock cycles is inserted 1 0 1 0 0 Wait with a length of 20 clock...

Page 271: ...0 1 1 Wait with a length of 19 clock cycles is inserted 1 0 1 0 0 Wait with a length of 20 clock cycles is inserted 1 0 1 0 1 Wait with a length of 21 clock cycles is inserted 1 0 1 1 0 Wait with a length of 22 clock cycles is inserted 1 0 1 1 1 Wait with a length of 23 clock cycles is inserted 1 1 0 0 0 Wait with a length of 24 clock cycles is inserted 1 1 0 0 1 Wait with a length of 25 clock cyc...

Page 272: ...ect These bits specify the number of wait cycles to be inserted into the first access during a normal write cycle or page write cycle Note Set these bits so that 1 WDON 2 0 WRON 2 0 CSWWAIT 4 0 or CSON 2 0 WRON 2 0 CSWWAIT 4 0 is satisfied CSRWAIT 4 0 Bits Normal Read Cycle Wait Select These bits specify the number of wait cycles to be inserted into the first access during a normal read cycle or p...

Page 273: ... always read as 0 The write value should always be 0 R W b6 to b4 CSWOFF 2 0 Write Access CS Extension Cycle Select b6 b4 0 0 0 No wait is inserted 0 0 1 Wait with a length of 1 clock cycle is inserted 0 1 0 Wait with a length of 2 clock cycles is inserted 0 1 1 Wait with a length of 3 clock cycles is inserted 1 0 0 Wait with a length of 4 clock cycles is inserted 1 0 1 Wait with a length of 5 clo...

Page 274: ... cycles is inserted R W b23 Reserved This bit is always read as 0 The write value should always be 0 R W b26 to b24 WDON 2 0 Write Data Output Wait Select b26 b24 0 0 0 No wait is inserted 0 0 1 Wait with a length of 1 clock cycle is inserted 0 1 0 Wait with a length of 2 clock cycles is inserted 0 1 1 Wait with a length of 3 clock cycles is inserted 1 0 0 Wait with a length of 4 clock cycles is i...

Page 275: ...e access mode Note Set these bits so that 1 WDOFF 2 0 CSWOFF 2 0 is satisfied RDON 2 0 Bits RD Assert Wait Select These bits specify the number of wait cycles to be inserted before the RD signal is asserted Note Set these bits so that the following conditions are satisfied CSON 2 0 RDON 2 0 CSRWAIT 4 0 in normal read access CSON 2 0 RDON 2 0 CSPRWAIT 2 0 in page read access WRON 2 0 Bits WR Assert...

Page 276: ...ote Set these bits so that the following conditions are satisfied CSON 2 0 RDON 2 0 CSRWAIT 4 0 in normal read access CSON 2 0 RDON 2 0 CSPRWAIT 2 0 in page read access CSON 2 0 WRON 2 0 CSWWAIT 4 0 in normal write access CSON 2 0 WRON 2 0 CSPWWAIT 2 0 in page write access Note Set each of these bits within a range of the restrictions described in section 11 5 5 1 Limitations at the Time of Normal...

Page 277: ...read from this bit 11 3 7 Bus Error Monitoring Enable Register BEREN TOEN Address 0008 1304h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 IGAEN Bit Symbol Bit Name Description R W 0 IGAEN Illegal Address Access Detection Enable 0 Illegal address access detection is disabled 1 Illegal address access detection is enabled R W 1 TOEN Time out Detection Enable 1 2 0 Time out detection is d...

Page 278: ...mbol Bit Name Description R W b0 CPEN CPU Bus Error Notification Control 0 Bus error interrupts are not conveyed to the CPU 1 Bus error interrupts are conveyed to the CPU R W b7 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W CPEN Bit CPU Bus Error Notification Control This bit controls whether the interrupt controller is 1 or is not 0 notified when bus errors...

Page 279: ... i 0 1 pins The WRi i 0 1 pins are not used Page access can occur in access to data in 32 bit units The situations in which page access occurs are indicated by the letter p in figures 11 3 and 11 4 The valid positions of data external to the chip and of control signals differ according to whether the endian is big or little Data Size 8 bits 16 bits 32 bits Access Address Number of Access 4n One Tw...

Page 280: ... and PWENB bits in CSiMOD 16 23 24 31 0 7 8 15 0 7 0 7 0 7 0 7 8 15 0 7 8 15 0 7 8 15 0 7 8 15 0 7 24 31 16 23 8 15 0 7 16 23 24 31 8 15 0 7 24 31 8 15 16 23 0 7 D8 Bus Cycle Unit of Data Address Figure 11 4 Data Alignment Big Endian in 16 Bit Bus Space 11 4 2 8 Bit Bus Space When an 8 bit bus space is selected by the BSIZE 1 0 bits in CSiCNT the address bus A23 to A0 output signals for access to ...

Page 281: ...its 8 bits 4n 3 4n 4 p p 4n 1 Four First 8 bits 8 bits 8 bits 8 bits 4n 1 4n 2 4n 3 4n 2 Four First 8 bits 8 bits 8 bits 8 bits 4n 2 4n 3 4n 4 4n 3 Four 8 bits 8 bits 8 bits 8 bits 4n 3 4n 4 4n 5 4n 3 4n 4 4n 5 4n 6 p p p p p p p p p Legend p Page access only when page access is enabled with the PRENB and PWENB bits in CSiMOD 16 23 24 31 0 7 8 15 0 7 0 7 0 7 0 7 8 15 0 7 8 15 0 7 8 15 0 7 8 15 0 7...

Page 282: ...its 4n 3 4n 4 p p 4n 1 Four First 8 bits 8 bits 8 bits 8 bits 4n 1 4n 2 4n 3 4n 2 Four First 8 bits 8 bits 8 bits 8 bits 4n 2 4n 3 4n 4 4n 3 Four First 8 bits 8 bits 8 bits 8 bits 4n 3 4n 4 4n 5 4n 3 4n 4 4n 5 4n 6 p p p p p p p p p Legend p Page access only when page access is enabled with the PRENB and PWENB bits in CSiMOD 8 15 0 7 0 7 0 7 0 7 0 7 8 15 0 7 8 15 0 7 8 15 0 7 8 15 0 7 8 15 0 7 8 1...

Page 283: ...ycle of reading or writing or for a cycle of page reading or page writing If the number of clock cycles in the period of waiting for a normal cycle of reading or writing or for a cycle of page reading or page writing is zero the clock cycle where bus access starts is the clock cycle where the strobe signal is valid The RD WRi and WR signals are negated in the next clock cycle after the cycle where...

Page 284: ... cycle is inserted as the period of negation of the CSi signal In the case of page access a period for negation of the CS signal is not inserted see figures 11 10 and 11 11 5 Tdw1 to Tdwn write data output extension clock cycles For write access if the setting for write data output extension wait is a value other than zero clock cycles of write data output extension are inserted from the cycle tha...

Page 285: ...nsertion of Recovery Cycles 11 5 1 1 Normal Access When the PRENB and PWENB bits in CSiMOD are set to 0 to disable page reading and page writing access respectively all bus access will take the form of normal read and write operations Even when the PRENB and PWENB bits in CSiMOD are set to 1 to enable page reading and page writing access respectively bus access other than page access will take the...

Page 286: ...trol CSn BC0 BC1 Legend n 0 to 7 Figure 11 8 Bus Timing Normal Write Operation Normal read cycle wait CSRWAIT 2 Read access CS extension cycle CSROFF 0 CS assert wait CSON 0 RD assert wait RDON 1 D1 D2 Data write WR0 WR1 WR A2 Normal write cycle wait CSWWAIT 2 Write access CS extension cycle CSWOFF 1 WR assert wait WRON 1 Write data output wait WDON 1 Write data output extension cycle WDOFF 1 A1 T...

Page 287: ...l CSn BC0 BC1 Data read RD Data bus D15 to D0 External bus clock BCLK Address A23 to A0 Normal read cycle wait CSRWAIT 2 RD assert wait RDON 1 Read access CS extension cycle CSROFF 1 CSRWAIT 2 Figure 11 10 Example of Normal Read Operation when Two Rounds of Bus Access are Generated in Response to a Single Request for Transfer A2 A1 Tw1 Tend Tw2 Tw1 Tw2 Tend Tn1 CSWOFF 1 WRON 1 Tn1 D1 D2 WDON 1 WDO...

Page 288: ...11 12 Example of Normal Read Operation when 16 Bit Bus Space is Accessed in 8 Bits Normal write cycle wait CSWWAIT 2 CS assert wait CSON 0 WR assert wait WRON 1 A2 A1 Tw1 Tend Tw2 Tw1 Tw2 Tend Tn1 CSWWAIT 2 CSWOFF 1 Tn1 Write data output wait WDON 1 D1 D2 Write access CS extension cycle CSWOFF 1 Write data output extension cycle WDOFF 1 Data write 1 WR1 Th Data write 0 WR0 Th WRON 1 WDOFF 1 WDON 1...

Page 289: ...e data output wait WDON 1 D1 D2 Write access CS extension cycle CSWOFF 1 WDON 1 Write data output extension cycle WDOFF 1 WDOFF 1 Chip select CSn Th Byte control 1 BC1 Byte control 0 BC0 Data write WR D1 D2 Th External bus clock BCLK Address A23 to A0 Data bus D15 to D8 Data bus D7 to D0 Legend n 0 to 7 Figure 11 14 Example of Normal Write Operation when 16 Bit Bus Space is Accessed in 16 Bits in ...

Page 290: ... master See figures 11 15 to 11 18 for the conditions under which page access occurs D0 D1 A0 A1 Page read cycle wait CSPRWAIT Read cycle wait CSRWAIT Read access CS extension cycle CSROFF RD assert wait RDON RD assert wait RDON CS assert wait CSON Tw1 Tpw1 Tnm Tpwn Tn1 Tw2 Tend Tend Th Twn Data bus D15 to D0 External bus clock BCLK Address A23 to A0 Chip select byte control CSn BC0 BC1 Legend n 0...

Page 291: ...g Figures 11 17 and 11 18 depict examples of operations for access to a 16 bit bus space in 32 bits The values of the wait control registers are example settings In practice the register settings will correspond to the specifications of connected devices D0 A0 A1 CSPRWAIT 1 CSRWAIT 1 CSROFF 1 RDON 1 Tw1 Tn1 Tend Tend A2 A3 Tw1 Tpw1 Tn1 Tend Tend D1 D2 D3 RDON 1 RDON 1 RDON 1 CSRWAIT 1 CSPRWAIT 1 C...

Page 292: ...d Tend Data write WR0 WR1 WR Th Accessed in 32 bits Write cycle wait CSWWAIT 1 CS assert wait CSON 0 WR assert wait WRON 1 Write data output wait WDON 1 Page write cycle wait CSPWWAIT 1 Write access CS extension cycle CSWOFF 1 Write data output extension cycle WDOFF 1 Accessed in 32 bits Data bus D15 to D0 External bus clock BCLK Address A23 to A0 Chip select byte control CSn BC0 BC1 Legend n 0 to...

Page 293: ... WAIT signal becomes high 11 5 2 2 Page Access The first data read or data write operation is the same as the normal read or write operation Sampling of the WAIT signal begins upon completion of the wait cycle Tend specified in the CSiWCNT1 register The bus cycle is extended while the WAIT signal is held low The wait cycle ends Tend at the next cycle after the WAIT signal becomes high With respect...

Page 294: ...rite data output extension cycle WDOFF Write data output wait WDON WR assert wait WRON Write data output extension cycle WDOFF Tw1 Tpw1 Tpwn Tw2 Tend Tend Twn Tdw1 Tdw1 Tend Tend Legend n 0 to 7 External wait WAIT Data write WR0 WR1 WR Data bus D15 to D0 External bus clock BCLK Address A23 to A0 Chip select byte control CSn BC0 BC1 Data read RD Figure 11 20 Example of External Wait Timing Page Wri...

Page 295: ... been performed in the preceding bus cycle In other words when a read access is made to CS0 and then to CS1 the number of recovery cycles to be inserted between these two accesses is determined by the PRCV 3 0 bits in CS0REC The clock cycles of recovery begin at the end of the preceding bus cycle i e when the CSi signal i 0 to 7 is negated From this point the selected period over which the CSi sig...

Page 296: ...completed Figure 11 22 shows an example of operation when the write buffer function is in use When this function is in use if the next operation after an external write is internal access the internal access access to on chip memory or a peripheral module is executed in parallel with the external write i e without waiting for completion of the latter operation Instruction bus Operand bus RAM ROM P...

Page 297: ... that Spans Areas of Address Space Single access operations that span areas of the address space are prohibited and operation in the case of attempts at such access is not guaranteed In cases where access to a single word or longword would produce access that crosses a boundary between areas split the instruction so that separate instructions are used for access to each of the areas 11 5 5 3 Restr...

Page 298: ... 5 5 Restriction on Instruction Code When the endian setting for an area is different from that for the chip no instruction code can be arranged in the area The instruction code should be arranged in the external address space whose endian setting is the same as that for the chip ...

Page 299: ... address space for which operation has been disabled CSiCNT EXENB 0 i 0 to 7 Access to illegal address ranges other than in areas for which operation has been disabled The address ranges where access will lead to illegal address access errors are indicated in table 11 10 11 6 1 2 Time out When the time out detection enable bit in the bus error enable register is set BEREN TOEN 1 bus access that is...

Page 300: ...a 007F 8000h to 007F 9FFFh FCU RAM 007F A000h to 007F BFFFh Reserved area 007F C000h to 007F C4FFh Peripheral I O registers 007F C500h to 007F FBFFh Reserved area 007F FC00h to 00FF FFFFh Peripheral I O registers 0080 0000h to 00DF FFFFh Reserved area 00E0 0000h to 00FF FFFFh On chip ROM dedicated area for writing 0100 0000h to 07FF FFFFh External address space CS1 to CS7 1 2 0800 0000h to 7FFF FF...

Page 301: ...m Single Data of a single operand is transferred per DMA transfer request Channel arbitration is made after a single operand transfer A DMA transfer request is necessary at each end of single operand transfer until the DMA transfer end Consecutive Data is transferred continuously in operand units until the DMA transfer end per DMA transfer request Channel arbitration is made after a single operand...

Page 302: ...s from the CPU Read write DMAC control circuit DMA transfer request arbitration Work registers Current transfer source address register Current transfer destination address register Current transfer byte count register Reload transfer source address register Reload transfer destination address register Reload transfer byte count register DMAC0 to DMAC3 Work transfer source address register Work tr...

Page 303: ...register B DMCRB 00h 0008 240Ch 8 DMA control register C DMCRC 00h 0008 240Dh 8 DMA control register D DMCRD 00h 0008 240Eh 8 DMA control register E DMCRE 00h 0008 240Fh 8 DMA current transfer source address register DMCSA xxxx xxxxh 0008 2010h 32 DMA current transfer destination address register DMCDA xxxx xxxxh 0008 2014h 32 DMA current transfer byte count register DMCBC 0xxx xxxxh 0008 2018h 32...

Page 304: ... address register DMCSA xxxx xxxxh 0008 2030h 32 DMA current transfer destination address register DMCDA xxxx xxxxh 0008 2034h 32 DMA current transfer byte count register DMCBC 0xxx xxxxh 0008 2038h 32 DMA reload transfer source address register DMRSA xxxx xxxxh 0008 2230h 32 DMA reload transfer destination address register DMRDA xxxx xxxxh 0008 2234h 32 DMA reload transfer byte count register DMR...

Page 305: ...ys read as 0 The write value should always be 0 R W b10 to b8 DMOD 2 0 Transfer Destination Address Addition Direction Select b10 b9 b8 0 0 0 Fixed 0 0 1 Plus 0 1 0 Minus 0 1 1 Rotate Do not write other values R W b11 Reserved This bit is always read as 0 The write value should always be 0 R W b14 to b12 SMOD 2 0 Transfer Source Address Addition Direction Select b14 b13 b12 0 0 0 Fixed 0 0 1 Plus ...

Page 306: ...s during DMA transfer When rotate is selected address is added in the plus direction and is returned to the value specified at the beginning of DMA transfer when single operand transfer is completed Transfer source and destination addresses increase or decrease according to the addition direction and data size settings as shown in table 12 3 Table 12 3 Address Increase Decrease According to Additi...

Page 307: ...ransfer Source Address Reload Function Select 0 Transfer source address reload function is not used 1 Transfer source address reload function is used R W b10 BRLOD Transfer Byte Count Reload Function Select 0 Transfer byte count reload function is not used 1 Transfer byte count reload function is used R W b23 to b11 Reserved These bits are always read as 0 The write value should always be 0 R W b2...

Page 308: ... compare match interrupt of 16 bit timer pulse unit 1 010111 TGI10A TPU10 input capture compare match interrupt of 16 bit timer pulse unit 1 011000 TGI11A TPU11 input capture compare match interrupt of 16 bit timer pulse unit 1 011001 RXI0 receive data full interrupt of serial communications interface SCI0 011010 TXI0 transmit data empty interrupt of serial communications interface SCI0 011011 RXI...

Page 309: ... used set the ECLR bit in DMCRC of DMACm to 1 the DEN bit is cleared to 0 at the end of DMA transfer to clear the DEN bit in DMCRE of DMACm to 0 DMA transfer disabled SRLOD Bit Transfer Source Address Reload Function Select This bit controls the transfer source address reload function When the SRLOD bit is set to 1 the value of the DMA reload transfer source address register DMRSA of DMACm is relo...

Page 310: ...is bit This bit is always read as 0 R W b7 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W DMCRB is used to control DMA transfer DSCLR Bit DMAC Internal Status Clear This bit initializes the internal status of the DMAC Setting the DSCLR bit to 1 when DMA has been suspended cancels the remainder of the DMA transfer and initializes the DMAC s internal transfer s...

Page 311: ... The DEN bit is cleared to 0 at the end of DMA transfer R W b7 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W DMCRC is used to control DMA transfer ECLR Bit DMA Transfer Enable Clear The ECLR bit controls behavior of the DEN bit in DMCRE of the given DMACm at the end of DMA transfer When the value of the ECLR bit is 1 the DEN bit is cleared to 0 at the end of...

Page 312: ...sfer requests the program generates a DMA transfer request by writing 1 to this bit If software triggering is not specified as a source of DMA transfer requests the program should not write 1 to this bit Write 0 to the DREQ bit while data transfer is not in progress i e while the DMAC is stopped or DMA transfer is disabled Writing of 1 can proceed regardless of the state of DMA transfer The DREQ b...

Page 313: ...ed These bits are always read as 0 The write value should always be 0 R W DMCRE is used to control DMA transfer DEN Bit DMA Transfer Enable The DEN bit enables DMA transfer While the ECLR bit is 1 the DEN bit is automatically cleared to 0 at the end of DMA transfer When the DEN bit is cleared to 0 in operand transfer mode DMA transfer on the given channel is suspended after the current single oper...

Page 314: ...m during data transfer but set it while the DMAC is not active or DMA transfer is disabled Access the DMCSA register of DMACm with 32 bits Write a multiple of 2 for 16 bit data size or a multiple of 4 for 32 bit data size to this register so that b31 to b0 correspond to A31 to A0 The value written to this register is transferred to the work register in the DMAC core at the beginning of DMA transfe...

Page 315: ... DMACm during data transfer but set it while the DMAC is not active or DMA transfer is disabled Access the DMCDA register of DMACm with 32 bits Write a multiple of 2 for 16 bit data size or a multiple of 4 for 32 bit data size to this register so that b31 to b0 correspond to A31 to A0 The value written to this register is transferred to the work register in the DMAC core at the beginning of DMA tr...

Page 316: ...t set it while the DMAC is not active or DMA transfer is disabled Access the DMCBC register of DMACm with 32 bits Write a multiple of 2 for 16 bit data size or a multiple of 4 for 32 bit data size to this register Writing 0000000h to this register makes the transfer byte count 64 Mbytes The value written to this register is transferred to the work register in the DMAC core at the beginning of DMA ...

Page 317: ...rite a multiple of 2 for 16 bit data size or a multiple of 4 for 32 bit data size to this register so that b31 to b0 correspond to A31 to A0 12 2 11 DMA Reload Transfer Destination Address Register DMRDA Addresses DMAC0 DMRDA 0008 2204h DMAC1 DMRDA 0008 2214h DMAC2 DMRDA 0008 2224h DMAC3 DMRDA 0008 2234h b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5 Value after reset x x x x x x x x x x x ...

Page 318: ...et the number of DMA transfer bytes to be reloaded to the DMCBC register of DMACm 0000000h to 3FFFFFFh R W b31 to b26 Reserved These bits are always read as 0 The write value should always be 0 R W DMRBC is used to set the number of DMA transfer bytes to be reloaded to the DMCBC register of DMACm Access the DMRBC register of DMACm with 32 bits When the BRLOD bit in DMCRA of DMACm is set to 1 the t...

Page 319: ...alue should always be 0 R W b4 DINTM3 DMA3 Interrupt Enable 0 DMAm interrupts are disabled 1 DMAm interrupts are enabled R W b5 DINTM2 DMA2 Interrupt Enable R W b6 DINTM1 DMA1 Interrupt Enable R W b7 DINTM0 DMA0 Interrupt Enable R W DMICNT is used to enable a DMAm m 0 to 3 interrupt request DMTENDm DINTMn Bits DMAm Interrupt Enable m 0 to 3 Setting the DINTMm bit to 1 enables a DMAm interrupt requ...

Page 320: ... is cleared to 0 during DMA transfer in operand transfer mode DMA transfer of all channels is suspended after the ongoing single operand transfer is completed The DMA transfer is restarted by setting this bit to 1 again In nonstop transfer mode DMA transfer is not suspended by clearing the DMST bit to 0 and continues until the DMA transfer is completed To make transitions to the module stop functi...

Page 321: ...r or nonstop transfer R b5 DASTS2 Channel 2 Arbitration Status Flag R b6 DASTS1 Channel 1 Arbitration Status Flag R b7 DASTS0 Channel 0 Arbitration Status Flag R DMASTS indicates data transfer status of each channel DASTSm Flag Channel m Arbitration Status Flag m 0 to 3 When data transfer single operand transfer or nonstop transfer of channel m is started the corresponding DASTSm flag is set to 1 ...

Page 322: ...ET indicates the DMA transfer end of each channel DEDETm Flags Channel m DMA Transfer End Detect Flags m 0 to 3 Upon completion of DMA transfer of channel m the DEDETm flag is set to 1 Once the DEDETm flag is set to 1 it is not cleared to 0 automatically To clear the DEDETm flag to 0 write 1 to the flag by the program This written value of 1 is not retained Writing 0 to these bits has no effect To...

Page 323: ...ble due to the relation between the clock and the timing of access In such cases divided up the data for transfer by the DMAC into smaller units and handle transfer in these units so that the CPU and DTC become able to accept access requests when transfer completed interrupts are conveyed to the CPU and DTC For details refer to section 11 Bus Figure 12 2 shows an example of how bus mastership pass...

Page 324: ...ime single operand transfer is completed Byte count corresponding to single operand data count bit length 01b Consecutive operand transfer Single operand data is transferred during DMA transfer Data is transferred in operand units until DMA transfer ends Channel arbitration is made each time single operand transfer is completed A DMA transfer request is generated first only once Byte count specifi...

Page 325: ...flag R W R W R W R W R W R W Channel arbitration Channel arbitration Channel arbitration Channel arbitration DMEDET DEDETm flag Channel m DMACm DMCBC register Single data DMACm DMCRD DREQ bit DMASTS DASTSm flag 0000000h R W R W R W R W Channel arbitration Channel arbitration DMEDET DEDETm flag R W R W R W R W R W 0000000h R W Channel arbitration 0000006h 0000004h R W R W R W R W R W R W Channel ar...

Page 326: ...ddress addition direction select Transfer source address addition direction select Transfer data size select Operand transfer data count select DMA activation source Transfer destination address reload function select Transfer source address reload function select Transfer byte count reload function select Transfer system select DMACm DMCRE DEN bit 0 DMA transfer disabled Start initial settings Se...

Page 327: ...to 1 data transfer is in progress 12 3 5 Ending DMA Transfer When the DMCBC register value of DMACm is decreased to 0000000h DMA transfer of channel m m 0 to 3 ends and the DMAC performs the following processing The DEDETm flag in DMEDET is set to 1 DMA transfer end detected When the DINTMm bit in DMICNT is 1 interrupts enabled a DMAm interrupt request DMTENDm request occurs When the value of the ...

Page 328: ... the DMAC to the module stop state or of the overall device to all module clock stop mode software standby mode or deep software standby mode clear the DMST bit to 0 stopping the DMAC 2 Restarting DMA transfer Suspended DMA transfer on a channel is restarted by setting the DMST bit in DMSCNT or the DEN bit in DMCRE of the given DMACm to 1 After returning the DMAC from the module stop state or the ...

Page 329: ...that the corresponding source of interrupt requests acts as a source of DMA transfer requests generation of the conditions for the selected request leads to the generation of a DMA transfer request When a DMA transfer request is detected the DREQ bit in DMCRD of DMACm is set to 1 to indicate the presence of the DMA transfer request and the value of the DREQ remains unchanged even if the input leve...

Page 330: ... value to a reload register before the data transfer ends the next transfer can be prepared without affecting the current register engaged in DMA transfer To use the reload function write data to the corresponding reload registers and current registers Set reload registers to be used before the final data transfer starts If they are set after the final data transfer starts the settings may not be ...

Page 331: ...rce rotate Transfer destination plus Figure 12 7 Example of Rotate Transfer 12 4 Interrupts When the DINTMm bit m 0 to 3 in DMICNT is set to 1 DMAm interrupts enabled a DMAm interrupt request DMTENDm is generated upon completion of channel m DMA transfer Figure 12 8 shows the schematic logic diagram of interrupt outputs To use a DMAm interrupt write 1 to the DEDETm flag in DMEDET of a channel in w...

Page 332: ...ng 1 to all bits in MSTPCRA and MSTPCRB including the MSTPA28 bit module stop bit for the DMAC and confirming that 1 has been written to all bits of the MSTPCRA and MSTPCRB registers executing a WAIT instruction causes a transition to the all module clock stop mode However if DMA transfer is in progress at the time the WAIT instruction is executed the transition to all module clock stop mode becom...

Page 333: ...EN bit in DMCRE of DMACm to 1 DMA transfer enabled for the selected channel 5 The DREQ bit in DMCRD of DMACm varies with the presence or absence of DMA transfer request regardless of the setting of the DMST bit in DMSCNT and the DEN bit in DMCRE of DMACm Unless software trigger is selected as a DMA activation source do not write 1 to the DREQ bit by the program 6 Set each address register and tran...

Page 334: ...3 longwords short address mode or in 4 longwords full address mode In short address mode transfer source address and transfer destination address can be specified with 24 bits and a 16 Mbyte address space can be directly specified for repeat transfer In full address mode transfer source address and transfer destination address can be specified with 32 bits and a 4 Gbyte address space can be direct...

Page 335: ...nal bus Register control MRA MRB CRA CRB SAR DAR Bus interface Startup control DTC response control Start request Vector number DTC response Stop request External bus interface External bus Bus master arbitrator Transfer data mode Interrupt control unit 8 20 Internal main bus 2 DTCCR DTCVBR DTCADMOD DTCST Vector base address Figure 13 1 Block Diagram of the DTC ...

Page 336: ...able 13 2 Registers of the DTC Register Name Symbol Value after Reset Address Access Size DTC mode register A MRA xxh 8 bits DTC mode register B MRB xxh 8 bits DTC source address register SAR xxxxxxxxh 32 bits DTC destination address register DAR xxxxxxxxh 32 bits DTC transfer count register A CRA xxxxh 16 bits DTC transfer count register B CRB xxxxh 16 bits DTC control register DTCCR 00h 0008 740...

Page 337: ... when SZ 1 0 bits 00b 2 when SZ 1 0 bits 01b 4 when SZ 1 0 bits 10b 1 1 SAR value is decremented after data transfer 1 when SZ 1 0 bits 00b 2 when SZ 1 0 bits 01b 4 when SZ 1 0 bits 10b b5 b4 SZ 1 0 DTC Data Transfer Size b5 b4 0 0 Byte transfer 0 1 Word transfer 1 0 Longword transfer 1 1 Setting prohibited b7 b6 MD 1 0 DTC Mode b7 b6 0 0 Normal transfer mode 0 1 Repeat transfer mode 1 0 Block tra...

Page 338: ...block area 1 Source side is repeat area or block area b5 DISEL DTC Interrupt Select 0 An interrupt request to the CPU is generated when specified data transfer is completed 1 An interrupt request to the CPU is generated each time DTC data transfer is performed b6 CHNS DTC Chain Transfer Select 0 Chain transfer is performed continuously 1 Chain transfer is performed only when the transfer counter i...

Page 339: ... x x x x x b20 b31 b24 b23 b19 b18 b17 b16 b30 b29 b28 b27 b26 b25 b22 b21 Legend x Undefined SAR is used to set the transfer source start address In full address mode 32 bits are valid In short address mode lower 24 bits are valid and upper 8 bits b31 to b24 are ignored The address of this register is extended by the value specified by b23 SAR cannot be accessed directly from the CPU 13 2 4 DTC D...

Page 340: ...er depends on transfer mode CRA cannot be accessed directly from the CPU 1 Normal transfer mode MD 1 0 bits in MRA 00b CRA functions as a 16 bit transfer counter in normal transfer mode The transfer count is 1 65535 and 65536 when the set value is 0001h FFFFh and 0000h respectively The CRA value is decremented 1 at each data transfer 2 Repeat transfer mode MD 1 0 bits in MRA 01b The CRAH register ...

Page 341: ...stop request is generated 1 A DTC transfer stop request is generated R b2 b1 Reserved These bits are read as 0 The write value should be 0 R W b3 RCHNE Chain Transfer Enable after DTC Repeat Transfer 0 Chain transfer after repeat transfer is disabled 1 Chain transfer after repeat transfer is enabled R W b4 RRS DTC Transfer Data Read Skip Enable 0 Transfer data read is not skipped 1 Transfer data r...

Page 342: ...unter is rewritten RRS Bit DTC Transfer Data Read Skip Enable The DTC vector number is always compared with the vector number in the previous startup process When these vector numbers match and the RRS bit is set to 1 DTC data transfer is performed without reading the transferred data However when the previous transfer was chain transfer the transferred data is always read regardless of the value ...

Page 343: ...b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 DTCST Bit Symbol Bit Name Description R W b0 DTCST DTC Module Start 0 DTC module stop 1 DTC module start R W b7 to b1 Reserved These bits are read as 0 The write value should be 0 R W DTCST is used to start or stop the DTC module DTCST Bit DTC Module Start Set the DTCST bit to 1 to enable the DTC to accept start requests When this bit is cl...

Page 344: ...sfer data can be allocated with 3 longwords short address mode or 4 longwords full address mode Use the SHORT bit in DTCADMOD to select short address mode SHORT bit 1 or full address mode SHORT bit 0 Figure 13 2 shows the allocation of transfer data in the data area The DTC reads the transfer data start address for each startup source and then reads the transfer data from this start address Figure...

Page 345: ...6 Feb 20 2013 Transfer data n start address Vector table DTC vector address 4n Transfer data 1 4 bytes Transfer data 2 Transfer data n Upper DTCVBR Lower Vector number 4 Transfer data 2 start address Transfer data 1 start address 4 4 bytes Figure 13 3 DTC Vector Table and Transfer Data ...

Page 346: ...104h ISELR065 IRQ2 66 0108h ISELR066 IRQ3 67 010Ch ISELR067 IRQ4 68 0110h ISELR068 IRQ5 69 0114h ISELR069 IRQ6 70 0118h ISELR070 IRQ7 71 011Ch ISELR071 IRQ8 72 0120h ISELR072 IRQ9 73 0124h ISELR073 IRQ10 74 0128h ISELR074 IRQ11 75 012Ch ISELR075 IRQ12 76 0130h ISELR076 IRQ13 77 0134h ISELR077 IRQ14 78 0138h ISELR078 IRQ15 79 013Ch ISELR079 AD0 ADI0 98 0188h ISELR098 AD1 ADI1 99 018Ch ISELR099 AD2 ...

Page 347: ... 159 027Ch ISELR159 TPU10 TGI10A 161 0284h ISELR161 TGI10B 162 0288h ISELR162 TPU11 TGI11A 167 029Ch ISELR167 TGI11B 168 02A0h ISELR168 TMR0 CMIA0 174 02B8h ISELR174 CMIB0 175 02BCh ISELR175 TMR1 CMIA1 177 02C4h ISELR177 CMIB1 178 02C8h ISELR178 TMR2 CMIA2 180 02D0h ISELR180 CMIB2 181 02D4h ISELR181 TMR3 CMIA3 183 02DCh ISELR183 CMIB3 184 02E0h ISELR184 DMAC DMTEND0 198 0318h ISELR198 DMTEND1 199 ...

Page 348: ...Activation Request Generation Source Activation Source Vector Number DTC Vector Address Offset ISELRi Register of the ICU Priority SCI6 RXI6 239 03BCh ISELR239 High TXI6 240 03C0h ISELR240 RIIC0 RXI0 247 03DCh ISELR247 TXI0 248 03E0h ISELR248 RIIC1 RXI1 251 03ECh ISELR251 TXI1 252 03F0h ISELR252 Low ...

Page 349: ...ize Transferred on a Single Transfer Request Increment Decrement of Memory Address Settable Transfer Count Normal transfer mode One byte word longword Incremented decremented by 1 2 or 4 or address fixed 1 to 65536 Repeat transfer mode 1 One byte word longword Incremented decremented by 1 2 or 4 or address fixed 1 to 256 3 Block transfer mode 2 Block size specified in CRAH 1 to 256 bytes words lon...

Page 350: ...er data Write transfer data Clear startup source flag Clear corresponding bit in the ISELRi register of the ICU An interrupt to the CPU is generated START END Match and RRS bit 1 Next transfer Update transfer data start address Transfer counter 0 or DISELbit 1 NO NO NO NO NO YES YES YES YES YES Compare vector numbers Match Read DTC vector Mismatch RRS bit 0 Figure 13 4 Operation Flowchart of the D...

Page 351: ...est to the CPU 0 1 1 0 0 0 Other than 0 Ends after the second transfer 0 0 0 2 Ends after the second transfer with an interrupt request to the CPU 0 1 1 1 0 Other than 0 Ends after the first transfer 1 1 0 2 0 0 Other than 0 Ends after the second transfer 0 0 0 2 Ends after the second transfer with an interrupt request to the CPU 0 1 1 1 1 Other than 0 Ends after the first transfer with an interru...

Page 352: ...evious block transfer transfer data is always read regardless of the value of RRS bit Figure 13 5 shows an example of transfer data read skip To update the vector table and transfer data set the RRS bit to 0 update the vector table and transfer data and then set the RRS bit to 1 When the RRS bit is set to 0 the retained vector number is discarded and the vector table and transfer data that are upd...

Page 353: ...back skip conditions and applicable registers The CRA and CRB registers are always written back independently of the setting of short address mode or full address mode Furthermore in full address mode write back of the MRA and MRB registers are always skipped Table 13 6 Transfer Data Write Back Skip Conditions and Applicable Registers SM 1 0 Bits in MRA DM 1 0 Bits in MRB SAR Register DAR Register...

Page 354: ...r Table 13 7 lists register functions in normal transfer mode and figure 13 6 shows the memory map of normal transfer mode Table 13 7 Register Functions in Normal Transfer Mode Register Description Value Written Back by Writing Transfer Data SAR Transfer source address Increment decrement fixed DAR Transfer destination address Increment decrement fixed CRA Transfer count A CRA 1 CRB Transfer count...

Page 355: ...s not become 00h which inhibits generation of interrupt request to the CPU when the DISEL bit in MRB is set to 0 an interrupt request to the CPU is generated when specified data transfer is completed Table 13 8 lists the register functions in repeat transfer mode and figure 13 7 shows the memory map of repeat transfer mode Table 13 8 Register Functions in Repeat Transfer Mode Register Description ...

Page 356: ...356 of 1006 Feb 20 2013 SAR Transfer source data area set to repeat area DAR Transfer Transfer destination data area Data 1 Data 2 Data 3 Data 4 Data 1 Data 2 Data 3 Data 4 Data 1 Data 2 Data 3 Data 4 Figure 13 7 Memory Map of Repeat Transfer Mode Transfer Source Repeat Area ...

Page 357: ...de enables an interrupt request to the CPU to be generated at the end of specified count block transfer Table 13 9 lists register functions in block transfer mode and figure 13 8 shows the memory map of block transfer mode Table 13 9 Register Functions in Block Transfer Mode Register Description Value Written Back by Writing Transfer Data SAR Transfer source address When DTS bit in MRB is 0 Increm...

Page 358: ... value is 0 but chain transfer is performed instead based on the next transfer information When the transfer counter value is not 0 the interrupt is issued to the CPU and the interrupt source flag as the startup source is cleared by setting the DISEL bit in MRB to 1 In chain transfer the interrupt is issued to the CPU or the interrupt source flag as the startup source is cleared upon transfer comp...

Page 359: ...ing the transfer control information R W i DTC vector number interrupt vector number Figure 13 10 Example of DTC Operation Timing 1 Short Address Mode Normal Transfer Mode Repeat Transfer Mode System clock Access by DTC Reading the vector Reading the transfer control information Transferring data Writting the transfer control information R W ICU IRi Request for DTC activation R W R W i DTC vector ...

Page 360: ...g data Writting the transfer control information R W R W ICU IRi i DTC vector number interrupt vector number Figure 13 12 Example of DTC Operation Timing 3 Short Address Mode Chain Transfer System clock Request for DTC activation Access by DTC Reading the vector Reading the transfer control information Transferri ng data Writting the transfer control information R W ICU IRi i DTC vector number int...

Page 361: ... or DAR is set to address fixed mode 5 When SAR and DAR are set to address fixed mode Legend P Block size set by CRAH and CRAL V Access cycles for the vector information data storing destination C Access cycles for the transfer information data storing destination R Access cycles for the data read destination W Access cycles for the data write destination V C R and W values depend on the access de...

Page 362: ...te transfer data see section 13 3 1 Allocating Transfer Data and DTC Vector Table 3 Set transfer data start addresses in the DTC vector table For how to set the DTC vector table see section 13 3 1 Allocating Transfer Data and DTC Vector Table 4 Set ing the RRS bit in DTCCR to 1 can skip the second and the subsequent transfer data read cycles for continuous DTC activation due to the same interrupt ...

Page 363: ... set to any value 2 The address where the transfer control information for use with the RXI starts is set in the vector table for the DTC 3 Set 01b in the corresponding ICU ISELRi register and 1 to the ICU IERi IENj bit Set the DTCST DTCST bit to 1 4 Set the SCI for the prescribed reception mode Enable reception completed interrupts by setting the SCR RIE bit in the given SCIm to 1 Also so that fu...

Page 364: ...ess MRA DM 1 0 00b transfer in normal mode MRA MD 1 0 00b and word sized transfer MRA SZ 1 0 01b Set the SAR register to the first address of the data table the DAR register to the address of the TPUm TGRA register and the CRA register to the size of the data table The CRB register can be set to any value 3 Place the transfer control information for use in transfer to the TPU immediately after the...

Page 365: ...r mode transfer source repeat area for re setting the transfer destination address of the first data transfer Specify the upper 8 bits of DAR in the first transfer data area for the transfer destination At this time set CHNE bit 0 chain transfer disabled in MRB and DISEL bit 0 an interrupt request to the CPU is generated when specified data transfer is completed in MRB When setting the input buffe...

Page 366: ...20 Page 366 of 1006 Feb 20 2013 Transfer data allocated in the on chip memory space Chain transfer counter 0 Input circuit Input buffer First data transfer Transfer data Second data transfer Transfer data Upper 8 bits of DAR Figure 13 15 Chain Transfer when Counter 0 ...

Page 367: ...ermitting all module clock stop mode in MSTPCRA writing 1 to all the bits in MSTPCRA and MSTPCRB including the MSTPA27 bit transition of the DTC to the module stop state and then executing a WAIT instruction enables transition to the all module clock stop mode However if DTC operations are in progress when a WAIT instruction is executed the DTC can make a transition to the all module clock stop st...

Page 368: ...ng data at the MSB side and the CRB setting data at the LSB side regardless of endian and then write the data to lower address 0 1 0 MRA SAR MRB DAR CRA CRB 3 2 Allocation of transfer data to little endian area Short address mode 4 bytes Lower address 2 3 MRA SAR MRB DAR CRA CRB 0 1 Allocation of transfer data to big endian area Short address mode 4 bytes Lower address Address 4n 4 n 1 4 n 2 1 0 M...

Page 369: ... disable the input buffer The configuration of the I O ports differs with the package The 144 pin LQFP version has 15 I O ports ports 0 to 9 and A to E which handle 117 I O pins The 176 pin LFBGA version has 18 I O ports ports 0 to 9 and A to H which handle 140 I O pins 14 1 Overview Table 14 1 gives the specifications of the I O ports and table 14 2 lists I O ports and pin functions Table 14 1 Sp...

Page 370: ...I I O signals RIIC I O signals and A D converter inputs 0 P10 IRQ0 B All input functions 1 P11 SCK2 IRQ1 B All input functions 2 P12 RxD2 IRQ2 B All input functions 3 P13 ADTRG0 IRQ3 B TxD2 All input functions 4 P14 SDA1 TCLKA B IRQ4 B All input functions 5 P15 SCK3 SCL1 TCLKB B IRQ5 B All input functions 6 P16 SDA0 TCLKC B RxD3 IRQ6 B All input functions 7 P17 SCL0 TCLKD B ADTRG1 IRQ7 B TxD3 All ...

Page 371: ...Q8 B P40 IRQ8 B 1 P41 AN1 IRQ9 B P41 IRQ9 B 2 P42 AN2 IRQ10 B P42 IRQ10 B 3 P43 AN3 IRQ11 B P43 IRQ11 B 4 P44 AN4 IRQ12 B P44 IRQ12 B 5 P45 AN5 IRQ13 B P45 IRQ13 B 6 P46 AN6 IRQ14 B P46 IRQ14 B 7 P47 AN7 IRQ15 B P47 IRQ15 B Port 5 General I O port pins system clock outputs bus control I O signals and tracing I O signals 0 P50 WR0 WR All input functions 1 P51 WR1 BC1 All input functions 2 P52 RD Al...

Page 372: ...l input functions 3 P83 All input functions 4 P84 All input functions 5 P85 All input functions 6 P86 All input functions Port 9 General I O port pins and A D converter inputs 0 P90 AN8 P90 1 P91 AN9 P91 2 P92 AN10 P92 3 P93 AN11 P93 4 P94 AN12 P94 5 P95 AN13 P95 6 P96 AN14 P96 7 P97 AN15 P97 Port A General I O port pins address outputs TPU I O signals and PPG outputs 0 PA0 TIOCA6 A0 PO16 BC0 All ...

Page 373: ... bus control outputs and SCI I O signals 0 PC0 A16 All input functions 1 PC1 A17 All input functions 2 PC2 A18 All input functions 3 PC3 A19 All input functions 4 PC4 A20 All input functions 5 PC5 SCK5 A21 CS5 D All input functions 6 PC6 RxD5 A22 CS6 D All input functions 7 PC7 A23 CS4 D CS7 D TxD5 All input functions Port D General I O port pins and bidirectional data bus lines 0 PD0 D0 D0 PD0 1 ...

Page 374: ...unctions Port G General I O port pins 0 PF0 All input functions 1 PF1 All input functions 2 PF2 All input functions 3 PF3 All input functions 4 PF4 All input functions 5 PF5 All input functions 6 PF6 All input functions 7 PF7 All input functions Port H General I O port pins 0 PH0 All input functions 1 PH1 All input functions 2 PH2 All input functions 3 PH3 All input functions 4 PH4 All input funct...

Page 375: ...a direction register DDR 00h 0008 C003h 8 Data register DR 00h 0008 C023h 8 Port register PORT Undefined 0008 C043h 8 Input buffer control register ICR 00h 0008 C063h 8 P4 Data direction register DDR 00h 0008 C004h 8 Data register DR 00h 0008 C024h 8 Port register PORT Undefined 0008 C044h 8 Input buffer control register ICR 00h 0008 C064h 8 P5 Data direction register DDR 00h 0008 C005h 8 Data reg...

Page 376: ...er control register ICR 00h 0008 C06Ch 8 Open drain control register ODR 00h 0008 C08Ch 8 Pull up resistor control register PCR 00h 0008 C0CCh 8 PD Data direction register DDR 00h 0008 C00Dh 8 Data register DR 00h 0008 C02Dh 8 Port register PORT Undefined 0008 C04Dh 8 Input buffer control register ICR 00h 0008 C06Dh 8 Pull up resistor control register PCR 00h 0008 C0CDh 8 PE Data direction registe...

Page 377: ...r 1 PFCR1 00h 0008 C101h 8 Port function control register 2 PFCR2 00h 0008 C102h 8 Port function control register 3 PFCR3 00h 0008 C103h 8 Port function control register 4 PFCR4 00h 0008 C104h 8 Port function control register 5 PFCR5 00h 0008 C105h 8 Port function control register 6 PFCR6 00h 0008 C106h 8 Port function control register 7 PFCR7 00h 0008 C107h 8 Port function control register 8 PFCR...

Page 378: ...009h PA DDR 0008 C00Ah PB DDR 0008 C00Bh PC DDR 0008 C00Ch PD DDR 0008 C00Dh PE DDR 0008 C00Eh PF DDR 0008 C00Fh PG DDR 0008 C010h PH DDR 0008 C011h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0 Bit Symbol Bit Name Description R W b0 B0 Pm0 I O Select m 0 to 9 and A to H 0 An input pin 1 An output pin R W b1 B1 Pm1 I O Select R W b2 B2 Pm2 I O Select R W b3 B3 P...

Page 379: ...7 DR 0008 C027h P8 DR 0008 C028h P9 DR 0008 C029h PA DR 0008 C02Ah PB DR 0008 C02Bh PC DR 0008 C02Ch PD DR 0008 C02Dh PE DR 0008 C02Eh PF DR 0008 C02Fh PG DR 0008 C030h PH DR 0008 C031h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0 Bit Symbol Bit Name Description R W b0 B0 Pm0 Output Data Store m 0 to 9 and A to H Output data are stored R W b1 B1 Pm1 Output Data...

Page 380: ...C049h PA PORT 0008 C04Ah PB PORT 0008 C04Bh PC PORT 0008 C04Ch PD PORT 0008 C04Dh PE PORT 0008 C04Eh PF PORT 0008 C04Fh PG PORT 0008 C050h PH PORT 0008 C051h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset x x x x x x x x B7 B6 B5 B4 B3 B2 B1 B0 Bit Symbol Bit Name Description R W b0 B0 Pm0 m 0 to 9 and A to H Individual pin states of the corresponding port are reflected R b1 B1 Pm1 R b2 B2 Pm2 R b3 B3 ...

Page 381: ...fer Control R W b4 B4 Pm4 Input Buffer Control R W b5 B5 Pm5 Input Buffer Control R W b6 B6 Pm6 Input Buffer Control R W b7 B7 Pm7 Input Buffer Control R W Note For pins being used as input pins for peripheral modules set the corresponding bits to 1 Set the bits corresponding to pins that are not being used for their input functions or are being used as analog I O pins to 0 Each ICR controls the i...

Page 382: ...n in input pin state for the pins corresponding to bits where the value in Pm PCR is 1 input pull up resistor is turned on Table 14 4 summarizes the input pull up resistor states Table 14 4 Input Pull Up Resistor States Port Pin State Reset In Other Operations Port A Address output Disabled Peripheral module output Disabled Port output Disabled Port input peripheral module input Disabled Enabled D...

Page 383: ... Select R W b7 B7 Pm7 Output Type Select R W Each ODR is used to select an output type for the individual pins 14 2 7 Port Function Control Register0 PFCR0 Value after reset Address 0008 C100h b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E 0 Bit Symbol Bit Name Description R W b0 CS0E CS0 Enable 0 Designated as an I O port pin 1 Designated as the CSn output pin n 0 t...

Page 384: ...t b5 b4 0 0 CS6 A is output from P62 0 1 CS6 B is output from P61 1 0 CS6 C is output from P71 1 1 CS6 D is output from PC6 R W b7 b6 CS7S 1 0 CS7 Output Pin Select b7 b6 0 0 CS7 A is output from P63 0 1 CS7 B is output from P61 1 0 CS7 C is output from P71 1 1 CS7 D is output from PC7 R W PFCR1 is used to select a pin for each CSn output PFCR1 can designate output of the several CS signals to a s...

Page 385: ...ut waveform Access to CS5 area Idle cycle Access to CS6 area Figure 14 1 Timing for Output of CSn Signals to the Same Pin Table 14 5 Relationship between CS Output Pin Select Registers and Output Pins Output Select CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 PFCR2 CS2S PFCR2 CS3S PFCR1 CS4S 1 0 PFCR1 CS5S 1 0 PFCR1 CS6S 1 0 PFCR1 CS7S 1 0 P60 CS0 CS4 A CS5 B P61 CS1 CS2 B CS5 A CS6 B CS7 B P62 CS2 A CS6 A P63...

Page 386: ...CS2 A is output from P62 1 CS2 B is output from P61 R W b7 CS3S CS3 Output Pin Select 0 CS3 A is output from P63 1 CS3 B is output from P70 R W PFCR2 is used to select a pin for each CSn output n 2 and 3 CSnS Bit CSn Output Pin Select n 2 and 3 Each bit selects a pin for each CSn output when a CSn output is enabled the corresponding CSiE bit in PFCR0 is 1 Several CS signals may be output from the ...

Page 387: ... is enabled R W b2 A18E Address A18 Enable 0 A18 output is disabled 1 A18 output is enabled R W b3 A19E Address A19 Enable 0 A19 output is disabled 1 A19 output is enabled R W b4 A20E Address A20 Enable 0 A20 output is disabled 1 A20 output is enabled R W b5 A21E Address A21 Enable 0 A21 output is disabled 1 A21 output is enabled R W b6 A22E Address A22 Enable 0 A22 output is disabled 1 A22 output...

Page 388: ...enabled R W b2 A10E Address A10 Enable 0 A10 output is disabled 1 A10 output is enabled R W b3 A11E Address A11 Enable 0 A11 output is disabled 1 A11 output is enabled R W b4 A12E Address A12 Enable 0 A12 output is disabled 1 A12 output is enabled R W b5 A13E Address A13 Enable 0 A13 output is disabled 1 A13 output is enabled R W b6 A14E Address A14 Enable 0 A14 output is disabled 1 A14 output is ...

Page 389: ...ated as an I O port pin 1 P51 is designated as the WR 1 or BC1 output pin R W b7 Reserved This bit is read as 0 The write value should be 0 R W PFCR5 is used to select external clock input pins for the TPU TCLKS Bit TPU External Clock Input Pin Select This bit selects the external clock input pins for the TPU DHE Bit D15 to D8 Enable This bit enables or disables the input and output of data signal...

Page 390: ...and output compare are allocated to P23 and P22 respectively R W b5 TPUMS3A Multifunction Select 3A for TPU I O Pins 0 Output compare and input capture are allocated to P21 1 Input capture and output compare are allocated to P20 and P21 respectively R W b6 TPUMS4 Multifunction Select 4 for TPU I O Pins 0 Output compare and input capture are allocated to P25 1 Input capture and output compare are a...

Page 391: ...ut pin for TIOCA4 TPUMS5 Bit Multifunction Select 5 for TPU I O Pins This bit selects a multiplexed function for TIOCA5 Table 14 6 Correspondences between PFCR6 and TPUn TMDR Settings Input Capture Inputs and External Pins TPU0 TMDR ICSELD PFCR6 TPUMS0B TPU0 TGRC TPU0 TGRD Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCC0 P32 TIOCD0 P33 0 1 P33 TIOCD0 P33 1 0 P32 TIOCC0 ...

Page 392: ...23 1 0 P22 TIOCC3 P22 1 1 P23 TIOCC3 P23 TPU3 TMDR ICSELB PFCR6 TPUMS3A TPU3 TGRA TPU3 TGRB Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCA3 P21 TIOCB3 P20 0 1 P20 TIOCB3 P20 1 0 P21 TIOCA3 P21 1 1 P20 TIOCA3 P20 TPU4 TMDR ICSELB PFCR6 TPUMS4 TPU4 TGRA TPU4 TGRB Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCA4 P25 TIOCB4 P24 0 1 P24 TIOCB4 P2...

Page 393: ...and output compare are allocated to PB3 and PB2 respectively R W b5 TPUMS9A Multifunction Select 9A for TPU I O Pins 0 Output compare and input capture are allocated to PB0 1 Input capture and output compare are allocated to PB1 and PB0 respectively R W b6 TPUMS10 Multifunction Select 10 for TPU I O Pins 0 Output compare and input capture are allocated to PB4 1 Input capture and output compare are...

Page 394: ...ut pin for TIOCA10 TPUMS11 Bit Multifunction Select 11 for TPU I O Pins TPU This bit selects an input pin for TIOCA11 Table 14 7 Correspondences between PFCR7 and TPUn TMDR Settings and Input Capture Inputs and External Pins TPU6 TMDR ICSELD PFCR7 TPUMS6B TPU6 TGRC TPU6 TGRD Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCC6 PA2 TIOCD6 PA3 0 1 PA3 TIOCD6 PA3 1 0 PA2 TIOCC...

Page 395: ...2 TIOCC9 PB2 1 1 PB3 TIOCC9 PB3 TPU9 TMDR ICSELB PFCR7 TPUMS9A TPU9 TGRA TPU9 TGRB Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCA9 PB0 TIOCB9 PB1 0 1 PB1 TIOCB9 PB1 1 0 PB0 TIOCA9 PB0 1 1 PB1 TIOCA9 PB1 TPU10 TMDR ICSELB PFCR7 TPUMS10 TPU10 TGRA TPU10 TGRB Input Capture Input External Pin Input Capture Input External Pin 0 0 TIOCA10 PB4 TIOCB10 PB5 0 1 PB5 TIOCB10 PB5 ...

Page 396: ...pin 1 P42 is designated as the IRQ10 B input pin R W b3 ITS11 IRQ11 Pin Select 0 P03 is designated as the IRQ11 A input pin 1 P43 is designated as the IRQ11 B input pin R W b4 ITS12 IRQ12 Pin Select 0 P04 is designated as the IRQ12 A input pin 1 P44 is designated as the IRQ12 B input pin R W b5 ITS13 IRQ13 Pin Select 0 P05 is designated as the IRQ13 A input pin 1 P45 is designated as the IRQ13 B i...

Page 397: ...Q2 A input pin 1 P12 is designated as the IRQ2 B input pin R W b3 ITS3 IRQ3 Pin Select 0 P33 is designated as the IRQ3 A input pin 1 P13 is designated as the IRQ3 B input pin R W b4 ITS4 IRQ4 Pin Select 0 P34 is designated as the IRQ4 A input pin 1 P14 is designated as the IRQ4 B input pin R W b5 ITS5 IRQ5 Pin Select 0 PE5 is designated as the IRQ5 A input pin 1 P15 is designated as the IRQ5 B inp...

Page 398: ...eans Don t care Input from a pin to a peripheral module is enabled by setting the corresponding bit in the input buffer control register Pm ICR to 1 It is necessary to set the peripheral module to use the enabled input function For the peripheral module settings to use the input function see the section for the peripheral module Note When the input function is allocated to two or more external pin...

Page 399: ... SCI and the B3 bit in P0 DDR Module Name Pin Function Setting SCI I O Port SCK4_OE P0 DDR B3 SCI SCK4 output 1 I O port P03 output 0 1 P03 input initial value 0 0 5 P04 TMCI3 TxD4 IRQ12 A TDI The pin function is switched as shown below according to the combination of the register setting for the SCI and the B4 bit in P0 DDR Module Name Pin Function Setting SCI I O Port TxD4_OE P0 DDR B4 SCI TxD4 ...

Page 400: ...n P1 DDR Module Name Pin Function Setting SCI I O Port SCK2_OE P1 DDR B1 SCI SCK2 output 1 I O port P11 output 0 1 P11 input initial value 0 0 3 P12 RxD2 IRQ2 B The pin function is switched as shown below according to the value of the B2 bit in P1 DDR Module Name Pin Function Setting I O Port P1 DDR B2 I O port P12 output 1 P12 input initial value 0 4 P13 TxD2 ADTRG0 IRQ3 B The pin function is swi...

Page 401: ...CI RIIC I O Port SCK3_OE SCL1_OE P1 DDR B5 SCI SCK3 output 1 RIIC SCL1 I O 0 1 I O port P15 output 0 0 1 P15 input initial value 0 0 0 7 P16 TCLKC B RxD3 SDA0 IRQ6 B The pin function is switched as shown below according to the combination of the register setting for the RIIC and the B6 bit in P1 DDR Module Name Pin Function Setting RIIC I O Port SDA0_OE P1 DDR B6 RIIC SDA0 I O 1 I O port P16 outpu...

Page 402: ...tion is switched as shown below according to the combination of the register settings for the TPU and PPG and the B1 bit in P2 DDR Module Name Pin Function Setting TPU PPG I O Port TIOCA3_OE PO1_OE P2 DDR B1 TPU TIOCA3 output 1 PPG PO1 output 0 1 I O port P21 output 0 0 1 P21 input initial value 0 0 0 3 P22 PO2 TIOCC3 TMO0 SCK0 The pin function is switched as shown below according to the combinati...

Page 403: ...pin function is switched as shown below according to the combination of the register settings for the TPU and PPG and the B4 bit in P2 DDR Module Name Pin Function Setting TPU PPG I O Port TIOCB4_OE PO4_OE P2 DDR B4 TPU TIOCB4 output 1 PPG PO4 output 0 1 I O port P24 output 0 0 1 P24 input initial value 0 0 0 6 P25 PO5 TIOCA4 TMCI1 RxD1 The pin function is switched as shown below according to the ...

Page 404: ...OE P2 DDR B6 TPU TIOCA5 output 1 TMR TMO1 output 0 1 SCI TxD1 output 0 0 1 PPG PO6 output 0 0 0 1 I O port P26 output 0 0 0 0 1 P26 input initial value 0 0 0 0 0 8 P27 PO7 TIOCA5 TIOCB5 SCK1 The pin function is switched as shown below according to the combination of the register settings for the TPU SCI and PPG and the B7 bit in P2 DDR Module Name Pin Function Setting TPU SCI PPG I O Port TIOCB5_O...

Page 405: ...A The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG and the B1 bit in P3 DDR Module Name Pin Function Setting TPU PPG I O Port TIOCB0_OE PO9_OE P3 DDR B1 TPU TIOCB0 output 1 PPG PO9 output 0 1 I O port P31 output 0 0 1 P31 input initial value 0 0 0 3 P32 PO10 TIOCC0 TCLKA A IRQ2 A The pin function is switched as shown below accord...

Page 406: ...e pin function is switched as shown below according to the combination of the register settings for the TPU and PPG and the B4 bit in P3 DDR Module Name Pin Function Setting TPU PPG I O Port TIOCA1_OE PO12_OE P3 DDR B4 TPU TIOCA1 output 1 PPG PO12 output 0 1 I O port P34 output 0 0 1 P34 input initial value 0 0 0 6 P35 PO13 TIOCA1 TIOCB1 TCLKC A The pin function is switched as shown below accordin...

Page 407: ...I O Port TIOCA2_OE PO14_OE P3 DDR B6 TPU TIOCA2 output 1 PPG PO14 output 0 1 I O port P36 output 0 0 1 P36 input initial value 0 0 0 8 P37 PO15 TIOCA2 TIOCB2 TCLKD A The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG and the B7 bit in P3 DDR Module Name Pin Function Setting TPU PPG I O Port TIOCB2_OE PO15_OE P3 DDR B7 TPU TIOCB2 ou...

Page 408: ... according to the value of the B1 bit in P4 DDR Module Name Pin Function Setting I O Port P4 DDR B1 I O port P41 output 1 P41 input initial value 0 3 P42 AN2 IRQ10 B The pin function is switched as shown below according to the value of the B2 bit in P4 DDR Module Name Pin Function Setting I O Port P4 DDR B2 I O port P42 output 1 P42 input initial value 0 4 P43 AN3 IRQ11 B The pin function is switc...

Page 409: ...ing to the value of the B5 bit in P4 DDR Module Name Pin Function Setting I O Port P4 DDR B5 I O port P45 output 1 P45 input initial value 0 7 P46 AN6 IRQ14 B The pin function is switched as shown below according to the value of the B6 bit in P4 DDR Module Name Pin Function Setting I O Port P4 DDR B6 I O port P46 output 1 P46 input initial value 0 8 P47 AN7 IRQ15 B The pin function is switched as ...

Page 410: ...e combination of the port function control register PFCRm setting and the B1 bit in P5 DDR Module Name Pin Function Setting Bus Controller I O Port WR1 _OE BC1 _OE P5 DDR B1 Bus controller WR1 BC1 output 1 I O port P51 output 0 1 P51 input initial value 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 3 P52 RD The pin function is switched as shown below accord...

Page 411: ...ing to the combination of the register setting for the B4 bit in P5 DDR Module Name Pin Function Setting I O Port P5 DDR B4 I O port P54 output 1 P54 input initial value 0 6 P55 TRDATA1 The pin function is switched as shown below according to the value of the B5 bit in P5 DDR Module Name Pin Function Setting I O Port P5 DDR B5 I O port P55 output 1 P55 input initial value 0 7 P56 TRDATA2 The pin f...

Page 412: ...output 1 CS4 A output 1 CS5 B output 1 I O port P60 output 0 0 0 1 P60 input initial value 0 0 0 0 2 P61 CS1 CS2 B CS5 A CS6 B CS7 B The pin function is switched as shown below according to the combination of the operating mode the EXBE bit in SYSCR0 the register setting for the bus controller the port function control register m PFCRm setting and the B1 bit in P6 DDR Module Name Pin Function Sett...

Page 413: ...he EXBE bit in SYSCR0 the register setting for the bus controller the port function control register m PFCRm setting and the B3 bit in P6 DDR Module Name Pin Function Setting Bus Controller I O Port CS3 A_OE CS7 A_OE P6 DDR B3 Bus controller CS3 A output 1 CS7 A output 1 I O port P63 output 0 0 1 P63 input initial value 0 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYS...

Page 414: ...own below according to the register setting for the D A converter and the B6 bit in P6 DDR Module Name Pin Function Setting D A Converter I O Port DA0_OE P6 DDR B6 D A converter DA0 output 1 I O port P66 output 0 1 P66 input initial value 0 0 8 P67 DA1 The pin function is switched as shown below according to the register setting for the D A converter and the B7 bit in P6 DDR Module Name Pin Functi...

Page 415: ...d or disabled SYSCR0 EXBE 1 2 P71 CS4 C CS5 C CS6 C CS7 C The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the register setting for the bus controller the port function control register m PFCRm setting and the B1 bit in P7 DDR Module Name Pin Function Setting Bus Controller I O Port CS4 C_OE CS5 C_OE CS6 C_OE CS7 C_OE P7 DDR B1 Bus controller CS4 C...

Page 416: ...rt P74 output 1 P74 input initial value 0 6 P75 The pin function is switched as shown below according to the value of the B5 bit in P7 DDR Module Name Pin Function Setting I O Port P7 DDR B5 I O port P75 output 1 P75 input initial value 0 7 P76 IRQ14 A The pin function is switched as shown below according to the value of the B6 bit in P7 DDR Module Name Pin Function Setting I O Port P7 DDR B6 I O ...

Page 417: ...ow according to the value of the B1 bit in P8 DDR Module Name Pin Function Setting I O Port P8 DDR B1 I O port P81 output 1 P81 input initial value 0 3 P82 TRCLK The pin function is switched as shown below according to the value of the B2 bit in P8 DDR Module Name Pin Function Setting I O Port P8 DDR B2 I O port P82 output 1 P82 input initial value 0 4 P83 The pin function is switched as shown bel...

Page 418: ...rt P84 output 1 P84 input initial value 0 6 P85 The pin function is switched as shown below according to the value of the B5 bit in P8 DDR Module Name Pin Function Setting I O Port P8 DDR B5 I O port P85 output 1 P85 input initial value 0 7 P86 The pin function is switched as shown below according to the value of the B6 bit in P8 DDR Module Name Pin Function Setting I O Port P8 DDR B6 I O port P86...

Page 419: ...w according to the value of the B1 bit in P9 DDR Module Name Pin Function Setting I O Port P9 DDR B1 I O port P91 output 1 P91 input initial value 0 3 P92 AN10 The pin function is switched as shown below according to the value of the B2 bit in P9 DDR Module Name Pin Function Setting I O Port P9 DDR B2 I O port P92 output 1 P92 input initial value 0 4 P93 AN11 The pin function is switched as shown ...

Page 420: ...ing to the value of the B5 bit in P9 DDR Module Name Pin Function Setting I O Port P9 DDR B5 I O port P95 output 1 P95 input initial value 0 7 P96 AN14 The pin function is switched as shown below according to the value of the B6 bit in P9 DDR Module Name Pin Function Setting I O Port P9 DDR B6 I O port P96 output 1 P96 input initial value 0 8 P97 AN15 The pin function is switched as shown below ac...

Page 421: ...tput 0 0 0 1 I O port PA0 output 0 0 0 0 1 PA0 input initial value 0 0 0 0 0 Note Address output is enabled when PA DDR B0 1 in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 2 PA1 A1 PO17 TIOCA6 TIOCB6 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister settings for the PPG and TPU and the B1 bit in PA DDR Module Name ...

Page 422: ...tial value 0 0 0 0 Note Address output is enabled when PA DDR B2 1 in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 4 PA3 A3 PO19 TIOCC6 TIOCD6 TCLKF The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister settings for the PPG and TPU and the B3 bit in PA DDR Module Name Pin Function Setting Bus Controller TPU PPG I O Port...

Page 423: ...l value 0 0 0 0 Note Address output is enabled when PA DDR B4 1 in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 6 PA5 A5 PO21 TIOCA7 TIOCB7 TCLKG The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister settings for the PPG and TPU and the B5 bit in PA DDR Module Name Pin Function Setting Bus Controller TPU PPG I O Port A5...

Page 424: ...l value 0 0 0 0 Note Address output is enabled when PA DDR B6 1 in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 8 PA7 A7 PO23 TIOCA8 TIOCB8 TCLKH The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister settings for the PPG and TPU and the B7 bit in PA DDR Module Name Pin Function Setting Bus Controller TPU PPG I O Port A7...

Page 425: ...t 0 1 PPG PO24 output 0 0 1 I O port PB0 output 0 0 0 1 PB0 input initial value 0 0 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 2 PB1 A9 PO25 TIOCA9 TIOCB9 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister settings for the PPG and TPU the port function control register m PFCRm setting and the B1...

Page 426: ...tings for the PPG and TPU the port function control register m PFCRm setting and the B3 bit in PB DDR Module Name Pin Function Setting Bus Controller TPU PPG I O Port A11_OE TIOCD9_OE PO27_OE PB DDR B3 Bus controller Address output 1 TPU TIOCD9 output 0 1 PPG PO27 output 0 0 1 I O port PB3 output 0 0 0 1 PB3 input initial value 0 0 0 0 Note Enabled in expansion mode with on chip ROM disabled or di...

Page 427: ...gs for the PPG and TPU the port function control register m PFCRm setting and the B6 bit in PB DDR Module Name Pin Function Setting Bus Controller TPU PPG I O Port A14_OE TIOCA11_OE PO30_OE PB DDR B6 Bus controller Address output 1 TPU TIOCA11 output 0 1 PPG PO30 output 0 0 1 I O port PB6 output 0 0 0 1 PB6 input initial value 0 0 0 0 Note Enabled in expansion mode with on chip ROM disabled or dis...

Page 428: ...ording to the combination of the EXBE bit in SYSCR0 the rgister settings for the bus controller the port function control register m PFCRm setting and the B1 bit in PC DDR Module Name Pin Function Setting Bus Controller I O Port A17_OE PC DDR B1 Bus controller A17 output 1 I O port PC1output 0 1 PC1 input initial value 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYSCR0...

Page 429: ...r the bus controller the port function control register m PFCRm setting and the B4 bit in PC DDR Module Name Pin Function Setting Bus Controller I O Port A20_OE PC DDR B4 Bus controller A20 output 1 I O port PC4 output 0 1 PC4 input initial value 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 6 PC5 A21 SCK5 CS5 D The pin function is switched as shown below a...

Page 430: ...nitial value 0 0 0 Note Enabled in expansion mode with on chip ROM disabled or disabled SYSCR0 EXBE 1 8 PC7 A23 TxD5 CS4 D CS7 D The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0 the rgister setting for the bus controller the port function control register m PFCRm setting and the B7 bit in PC DDR Module Name Pin Function Setting Bus Controller SCI I...

Page 431: ...E 1 14 3 15 Port E PE 1 PE0 D8 PE1 D9 PE2 D10 PE3 D11 PE4 D12 PE5 D13 IRQ5 A PE6 D14 IRQ6 A PE7 D15 IRQ7 A The pin function is switched as shown below according to the combination of bus mode setting the EXBE bit in SYSCR0 the port function control register m PFCRm setting and the Bj bit j 0 to 7 in PE DDR Module Name Pin Function Setting Bus Controller I O Port Dn_E n 8 to 15 PE DDR Bn Bus contro...

Page 432: ...ow according to the value of the B1 bit in PF DDR Module Name Pin Function Setting I O Port PF DDR B1 I O port PF1 output 1 PF1 input initial value 0 3 PF2 The pin function is switched as shown below according to the value of the B2 bit in PF DDR Module Name Pin Function Setting I O Port PF DDR B2 I O port PF2 output 1 PF2 input initial value 0 4 PF3 The pin function is switched as shown below acc...

Page 433: ...rt PF4 output 1 PF4 input initial value 0 6 PF5 The pin function is switched as shown below according to the value of the B5 bit in PF DDR Module Name Pin Function Setting I O Port PF DDR B5 I O port PF5 output 1 PF5 input initial value 0 7 PF6 The pin function is switched as shown below according to the value of the B6 bit in PF DDR Module Name Pin Function Setting I O Port PF DDR B6 I O port PF6...

Page 434: ...B1 I O port PG1 output 1 PG1 input initial value 0 3 PG2 The pin function is switched as shown below according to the value of the B2 bit in PG DDR Module Name Pin Function Setting I O Port PG DDR B2 I O port PG2 output 1 PG2 input initial value 0 4 PG3 The pin function is switched as shown below according to the value of the B3 bit in PG DDR Module Name Pin Function Setting I O Port PG DDR B3 I O...

Page 435: ...rt PG5 output 1 PG5 input initial value 0 7 PG6 The pin function is switched as shown below according to the value of the B6 bit in PG DDR Module Name Pin Function Setting I O Port PG DDR B6 I O port PG6 output 1 PG6 input initial value 0 8 PG7 The pin function is switched as shown below according to the value of the B7 bit in PG DDR Module Name Pin Function Setting I O Port PG DDR B7 I O port PG7...

Page 436: ...B1 I O port PH1 output 1 PH1 input initial value 0 3 PH2 The pin function is switched as shown below according to the value of the B2 bit in PH DDR Module Name Pin Function Setting I O Port PH DDR B2 I O port PH2 output 1 PH2 input initial value 0 4 PH3 The pin function is switched as shown below according to the value of the B3 bit in PH DDR Module Name Pin Function Setting I O Port PH DDR B3 I O...

Page 437: ...rt PH5 output 1 PH5 input initial value 0 7 PH6 The pin function is switched as shown below according to the value of the B6 bit in PH DDR Module Name Pin Function Setting I O Port PH DDR B6 I O port PH6 output 1 PH6 input initial value 0 8 PH7 The pin function is switched as shown below according to the value of the B7 bit in PH DDR Module Name Pin Function Setting I O Port PH DDR B7 I O port PH7...

Page 438: ...CKE 1 0 01 or SMR GM 1 When SCMR SMIF 0 SMR CM 0 SCR CKE 1 0 01 or SMR CM 1 SCR CKE 1 0 3 SCI4 SCK4_OE SCK4 When SCMR SMIF 1 SMR GM 0 SCR CKE 1 0 01 or SMR GM 1 When SCMR SMIF 0 SMR CM 0 SCR CKE 1 0 01 or SMR CM 1 SCR CKE 1 0 4 SCI4 TxD4_OE TxD4 SCR TE 1 5 TMR3 TMO3_OE TMO3 TCSR OSA 1 0 01 10 11 or TCSR OSB 1 0 01 10 11 P1 0 1 SCI2 SCK2_OE SCK2 When SCMR SMIF 1 SMR GM 0 SCR CKE 1 0 01 or SMR GM 1 ...

Page 439: ...IF 1 SMR GM 0 SCR CKE 1 0 01 or SMR GM 1 When SCMR SMIF 0 SMR CM 0 SCR CKE 1 0 01 or SMR CM 1 SCR CKE 1 0 PPG0 PO2_OE PO2 NDERL NDER2 1 3 TPU3 TIOCD3_OE TIOCD3 TMDR BFB 0 TIORL IOD 3 0 TIORL IOD 1 0 01 10 11 PPG0 PO3_OE PO3 NDERL NDER3 1 4 TPU4 TIOCB4_OE TIOCB4 TIOR IOB 3 0 TIOR IOB 1 0 01 10 11 PPG0 PO4_OE PO4 NDERL NDER4 1 5 TPU4 TIOCA4_OE TIOCA4 TIOR IOA 3 0 TIOR IOA 1 0 01 10 11 PPG0 PO5_OE PO...

Page 440: ...OD 3 0 TIORL IOD 1 0 01 10 11 PPG0 PO11_OE PO11 NDERH NDER11 1 4 TPU1 TIOCA1_OE TIOCA1 TIOR IOA 3 0 TIOR IOA 1 0 01 10 11 PPG0 PO12_OE PO12 NDERH NDER12 1 5 TPU1 TIOCB1_OE TIOCB1 TIOR IOB 3 0 TIOR IOB 1 0 01 10 11 PPG0 PO13_OE PO13 NDERH NDER13 1 6 TPU2 TIOCA2_OE TIOCA2 TIOR IOA 3 0 TIOR IOA 1 0 01 10 11 PPG0 PO14_OE PO14 NDERH NDER14 1 7 TPU2 TIOCB2_OE TIOCB2 TIOR IOB 3 0 TIOR IOB 1 0 01 10 11 PP...

Page 441: ...S6CNT EXENB 1 SYSC CS7B_OE CS7 PFCR1 CS7S 1 0 01 SYSCR0 EXBE 1 PFCR0 CS7E 1 CS7CNT EXENB 1 2 SYSC CS2A_OE CS2 PFCR2 CS2S 0 SYSCR0 EXBE 1 PFCR0 CS2E 1 CS2CNT EXENB 1 SYSC CS6A_OE CS6 PFCR1 CS6S 1 0 00 SYSCR0 EXBE 1 PFCR0 CS6E 1 CS6CNT EXENB 1 3 SYSC CS3A_OE CS3 PFCR2 CS3S 0 SYSCR0 EXBE 1 PFCR0 CS3E 1 CS3CNT EXENB 1 SYSC CS7A_OE CS7 PFCR1 CS7S 1 0 00 SYSCR0 EXBE 1 PFCR0 CS7E 1 CS7CNT EXENB 1 4 SYSC ...

Page 442: ...OE TIOCC6 TMDR BFA 0 TIORL IOC 3 0 TIORL IOC 1 0 01 10 11 PPG1 PO 18_OE PO18 NDERL NDER18 1 SYSC A2_OE A2 SYSCR0 EXBE 1 PA DDR B2 1 3 TPU6 TIOCD6_OE TIOCD6 TMDR BFB 0 TIORL IOD 3 0 TIORL IOD 1 0 01 10 11 PPG1 PO 19_OE PO19 NDERL NDER19 1 SYSC A3_OE A3 SYSCR0 EXBE 1 PA DDR B3 1 4 TPU7 TIOCA7_OE TIOCA7 TIOR IOA 3 0 TIOR IOA 1 0 01 10 11 PPG1 PO 20_OE PO20 NDERL NDER20 1 SYSC A4_OE A4 SYSCR0 EXBE 1 P...

Page 443: ... 10 11 PPG1 PO26_OE PO26 NDERH NDER26 1 SYSC A10_OE A10 SYSCR0 EXBE 1 PFCR4 A10E 1 3 TPU9 TIOCD9_OE TIOCD9 TMDR BFB 0 TIORL IOD 3 0 TIORL IOD 1 0 01 10 11 PPG1 PO27_OE PO27 NDERH NDER27 1 SYSC A11_OE A11 SYSCR0 EXBE 1 PFCR4 A11E 1 4 TPU10 TIOCA10_OE TIOCA10 TIOR IOA 3 0 TIOR IOA 1 0 01 10 11 PPG1 PO28_OE PO28 NDERH NDER28 1 SYSC A12_OE A12 SYSCR0 EXBE 1 PFCR4 A12E 1 5 TPU10 TIOCB10_OE TIOCB10 TIOR...

Page 444: ...PFCR0 CS6E 1 CS6CNT EXENB 1 7 SYSC A23_OE A23 SYSCR0 EXBE 1 PFCR3 A23E 1 PC DDR B7 1 SCI5 TxD5_OE TxD5 SCR TE 1 SYSC CS4D_OE CS4 PFCR1 CS4S 1 0 11 SYSCR0 EXBE 1 PFCR0 CS4E 1 CS4CNT EXENB 1 SYSC CS7D_OE CS7 PFCR1 CS7S 1 0 11 SYSCR0 EXBE 1 PFCR0 CS7E 1 CS7CNT EXENB 1 PD 0 SYSC D0_E D0 SYSCR0 EXBE 1 1 SYSC D1_E D1 SYSCR0 EXBE 1 2 SYSC D2_E D2 SYSCR0 EXBE 1 3 SYSC D3_E D3 SYSCR0 EXBE 1 4 SYSC D4_E D4 ...

Page 445: ...e mode pins Boot mode P P C P P P P P P P P P P P P P P User boot mode P P C P P P P P P P P P P P P P P Single chip mode P P C P P P P P P P P P P P P P P Transition by the register Single chip mode P P C P P P P P P P P P P P P P P Expansion mode with on chip ROM enabled P C P C P C P C P C P C P C A P A P A C P A P D P D P P P Expansion mode with on chip ROM disabled P C P C P C P C P C P C P C...

Page 446: ...r to Vss via a pull down resistor respectively These pins can be left while Pm ICR is in the initial state the input buffer disabled P52 This pin is left open for the RD output P51 Connect this pin to Vcc via a pull up resistor or to Vss via a pull down resistor This pin can be left while Pm ICR is in the initial state the input buffer disabled P50 This pin is left open for the WR0 WR output P60 P...

Page 447: ...7 Port 3 P30 to P37 Port 5 P50 to P52 and P54 to P57 Port 6 P60 to P65 Port 7 P70 to P77 Port 8 P80 to P86 Port F PF0 to PF6 1 Port G PG0 to PG7 1 Port H PH0 to PH7 1 Internal bus Port 2 P20 to P27 ODR DDR DR Peripheral module output signal Enabling a peripheral module output 2 Internal bus Note 1 Not provided on the 144 pin LQFP Note 2 Control signal for NMOS open drain output Peripheral module i...

Page 448: ...CLK output signal ICR Port 4 P40 to P47 Port 9 P90 to P97 DDR DR Port 5 P53 Internal bus Analog input Internal bus Peripheral module input signal Port read input signal ICR Port read signal Port read input signal Port read signal AD input enable signal Figure 14 3 I O Port Configuration 2 ...

Page 449: ...us DA output enable signal Analog output Port A PA0 to PA7 Port B PB0 to PB7 PCR DDR DR Peripheral module output signal Enabling a peripheral module output Internal bus Port read input signal Port read signal Peripheral module input signal Port read input signal ICR Port read signal Figure 14 4 I O Port Configuration 3 ...

Page 450: ...ule output signal Enabling a peripheral module output 1 Internal bus Internal bus ODR External bus read access External bus read data Peripheral module input signal Port read input signal ICR Port read signal Peripheral module output signal Port read input signal ICR Port read signal Note 1 Control signal for NMOS open drain output Figure 14 5 I O Port Configuration 4 ...

Page 451: ...n Control Register PFCRn Each PFCRn controls an I O port When setting input or output functions for individual pins select a pin for the input or output and then enable or disable the input or output function If the levels for a pin before and after it has been switched to operate as an input differ from each other an internal edge is generated This may lead to operation that was not intended To a...

Page 452: ...lock Seven or eight types are provided for each channel Settable operations Waveform output at compare match Input capture function Counter clear operation Simultaneous writing to multiple timer counters TCNT Simultaneous clearing by compare match and input capture Simultaneous input output for registers by counter synchronous operation Maximum of 15 phase PWM output by combination with synchronou...

Page 453: ...nput capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture Compare match output Low output Poss ble Possible Possible Poss ble Possible Possible High output Poss ble Possible Possible Poss ble Possible Possible Toggle output Poss ble Possible Possible Poss ble Possible Possib...

Page 454: ...pture TGRA TGRB comparematchor input capture TGRA TGRB comparematchor input capture Not poss ble Not poss ble Interrupt sources 5 sources Comparematchor input capture 0A Comparematchor input capture 0B Comparematchor input capture 0C Comparematchor input capture 0D Overflow 4 sources Comparematchor input capture 1A Comparematchor input capture 1B Overflow Underflow 4 sources Comparematchor input c...

Page 455: ...r input capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture TGRy comparematchor input capture Compare match output Low output Poss ble Possible Possible Possible Possible Poss ble High output Poss ble Possible Possible Possible Possible Poss ble Toggle output Poss ble Possible Possible Possible Possible Pos...

Page 456: ...ot possible Not possible Interrupt sources 5 sources Comparematchor input capture 6A Comparematchor input capture 6B Comparematchor input capture 6C Comparematchor input capture 6D Overflow 4 sources Comparematchor input capture 7A Comparematchor input capture 7B Overflow Underflow 4 sources Comparematchor input capture 8A Comparematchor input capture 8B Overflow Underflow 5 sources Comparematchor...

Page 457: ...SR TGRA to TGRD TCNT Timer start register Timer synchronous register Timer control register Timer mode register Timer interrupt enable register Timer status register Timer counter Timer I O control registers H L TIORH TIORL Timer general registers A B C D Input output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 TPU3 TPU4 TPU5 TCLKA TCLKB TCLKC TCLKD PCLK 1 Clock input PCLK 4096 PC...

Page 458: ...imer synchronous register Timer control register Timer mode register Timer interrupt enable register Timer status register Timer counter Timer I O control registers H L TIORH TIORL Timer general registers A B C D Input output pins TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 TPU9 TPU10 TPU11 TCLKE TCLKF TCLKG TCLKH PCLK 1 Clock input PCLK 4096 PCLK 4 PCLK 16 PCLK 64 PCLK 256 PCLK 10...

Page 459: ... input output compare output PWM output pin TPU5 TIOCA5 I O TPU5 TGRA input capture input output compare output PWM output pin TIOCB5 I O TPU5 TGRB input capture input output compare output PWM output pin Unit 1 All TCLKE Input External clock E input pin TPU7 and TPU11 phase counting mode A phase input TCLKF Input External clock F input pin TPU7 and TPU11 phase counting mode B phase input TCLKG In...

Page 460: ...8 Timer interrupt enable register TIER 40h 0008 8124h 8 Timer status register TSR xxh 0008 8125h 8 Timer counter TCNT 0000h 0008 8126h 16 Timer general register A TGRA FFFFh 0008 8128h 16 Timer general register B TGRB FFFFh 0008 812Ah 16 TPU2 Timer control register TCR 00h 0008 8130h 8 Timer mode register TMDR 00h 0008 8131h 8 Timer I O control register TIOR 00h 0008 8132h 8 Timer interrupt enable...

Page 461: ...8168h 16 Timer general register B TGRB FFFFh 0008 816Ah 16 All Timer start register TSTRA 00h 0008 8100h 8 Timer synchronous register TSYRA 00h 0008 8101h 8 Unit 1 TPU6 Timer control register TCR 00h 0008 8180h 8 Timer mode register TMDR 00h 0008 8181h 8 Timer I O control register H TIORH 00h 0008 8182h 8 Timer I O control register L TIORL 00h 0008 8183h 8 Timer interrupt enable register TIER 40h ...

Page 462: ...0h 0008 81B6h 16 Timer general register A TGRA FFFFh 0008 81B8h 16 Timer general register B TGRB FFFFh 0008 81BAh 16 Timer general register C TGRC FFFFh 0008 81BCh 16 Timer general register D TGRD FFFFh 0008 81BEh 16 TPU10 Timer control register TCR 00h 0008 81C0h 8 Timer mode register TMDR 00h 0008 81C1h 8 Timer I O control register TIOR 00h 0008 81C2h 8 Timer interrupt enable register TIER 40h 0...

Page 463: ...he TPU has twelve TCR registers one for each channel TPUm TCR controls TPUm TCNT counter of each channel TPUm TCR settings should be made while TPUm TCNT counter operation is stopped TPSC 2 0 Bits Timer Prescaler Select These bits select the TCNT counter clock The clock source can be selected independently for each channel To select the external clock as the clock source set the bit in the data di...

Page 464: ...0 Internal clock counts on PCLK 16 0 1 1 Internal clock counts on PCLK 64 1 0 0 External clock counts on TCLKA or TCLKE pin input 1 0 1 External clock counts on TCLKB or TCLKF pin input 1 1 0 Internal clock counts on PCLK 256 1 1 1 TPU1 unit 0 Counts on TPU2 TCNT counter overflow underflow TPU7 unit 1 Counts on TPU8 TCNT counter overflow underflow Note This setting is invalid when TPU1 or TPU7 is ...

Page 465: ...nts on PCLK 16 0 1 1 Internal clock counts on PCLK 64 1 0 0 External clock counts on TCLKA or TCLKE pin input 1 0 1 External clock counts on TCLKC or TCLKG pin input 1 1 0 Internal clock counts on PCLK 1024 1 1 1 TPU4 unit 0 Counts on TPU5 TCNT counter overflow underflow TPU10 unit 1 Counts on TPU11 TCNT counter overflow underflow Note This setting is invalid when TPU4 or TPU10 is in phase countin...

Page 466: ...ter clearing for another channel performing synchronous clearing synchronous operation 2 Notes 1 When TGRC or TGRD is used as a buffer register TCNT counter is not cleared because the buffer register setting has priority and compare match input capture does not occur 2 Synchronous operation is selected by setting the SYNCi bit i 0 3 bit in TSYRm m A B to 1 Table 15 14 Bits CCLR 2 0 TPU1 TPU2 TPU4 ...

Page 467: ...Buffer Operation B 0 TPUm TGRB operates normally 1 TPUm TGRB and TPUm TGRD used together for buffer operation n 0 3 6 9 R W b6 ICSELB TGRB Input Capture Input Select 0 Input capture input source is TIOCBn pin 1 Input capture input source is TIOCAn pin n 0 to 11 R W b7 ICSELD 4 TGRD Input Capture Input Select 0 Input capture input source is TIOCDn pin 1 Input capture input source is TIOCCn pin n 0 ...

Page 468: ... Specifies whether TPUm TGRB m 0 3 6 9 is to normally operate or TPUm TGRB and TPUm TGRD m 0 3 6 9 are to be used together for buffer operation When TGRD is used as a buffer register TGRD input capture output compare is not generated ICSELB Bit TGRB Input Capture Input Select Selects the input capture input for TPUm TGRB m 0 to 11 This function allows measurement of high level width and period of ...

Page 469: ...OD 3 0 Bit Symbol Bit Name Description R W b3 to b0 IOC 3 0 TGRC Control See tables 15 21 and 15 22 R W b7 to b4 IOD 3 0 TGRD Control See tables 15 21 and 15 22 R W The TPU has four TIORH registers one for TPU0 TPU3 TPU6 and TPU9 and four TIORL registers one for TPU0 TPU3 TPU6 and TPU9 and also has eight TIOR registers one for TPU1 TPU2 TPU4 TPU5 TPU7 TPU8 TPU10 and TPU11 Thus the TPU has sixteen ...

Page 470: ...Feb 20 2013 IOA 3 0 Bits TGRA Control Select the function of TPUm TGRA m 0 to 11 IOB 3 0 Bits TGRB Control Select the function of TPUm TGRB m 0 to 11 IOC 3 0 Bits TGRC Control Select the function of TPUm TGRC m 0 3 6 9 IOD 3 0 Bits TGRD Control Select the function of TPUm TGRD m 0 3 6 9 ...

Page 471: ...7 TCNT count up count down 1 Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 0 6 Function TIOCBn Pin n 0 6 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial output is low output toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Init...

Page 472: ...urce is TPU6 TGRA compare match input capture Input capture at generation of TPU6 TGRA compare match input capture Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 1 7 Function TIOCBn Pin n 1 7 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial ou...

Page 473: ...is TIOCAn pin input capture at falling edge 1 x 1 x Capture input source is TIOCAn pin input capture at both edges Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 2 8 Function TIOCBn Pin n 2 8 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial ou...

Page 474: ... TCNT count up count down 1 Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 3 9 Function TIOCBn Pin n 3 9 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial output is low output toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initi...

Page 475: ...urce is TPU9 TGRA compare match input capture Input capture at generation of TPU9 TGRA compare match input capture Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 4 10 Function TIOCBn Pin n 4 10 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial ...

Page 476: ...is TIOCAn pin input capture at falling edge 1 x 1 x Capture input source is TIOCAn pin input capture at both edges Bits IOB 3 0 Description b7 b6 b5 b4 TPUm TGRB m 5 11 Function TIOCBn Pin n 5 11 Function 0 0 0 0 Output compare register Output disabled 0 0 0 1 Initial output is low output low output at compare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial ...

Page 477: ...are match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial output is low output toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is high output low output at compare match 0 1 1 0 Initial output is high output high output at compare match 0 1 1 1 Initial output is high output toggle output at compare match 1 0 0 0 Input capture register...

Page 478: ...pare match 0 0 1 0 Initial output is low output high output at compare match 0 0 1 1 Initial output is low output toggle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is high output low output at compare match 0 1 1 0 Initial output is high output high output at compare match 0 1 1 1 Initial output is high output toggle output at compare match 1 0 0 0 Input Capture registe...

Page 479: ...ED 1 TGRD Interrupt Enable 0 Interrupt requests TGImD disabled 1 Interrupt requests TGImD enabled m 0 3 6 9 R W b4 TCIEV Overflow Interrupt Enable 0 Interrupt requests TCImV disabled 1 Interrupt requests TCImV enabled m 0 to 11 R W b5 TCIEU 2 Underflow Interrupt Enable 0 Interrupt requests TCImU disabled 1 Interrupt requests TCImU enabled m 1 2 4 5 7 8 10 11 R W b6 Reserved This bit is read as 1 T...

Page 480: ...sts TGImC m 0 3 6 9 TGIED Bit TGRD Interrupt Enable Enables disables interrupt requests TGImD m 0 3 6 9 TCIEV Bit Overflow Interrupt Enable Enables disables interrupt requests TCImV m 0 to 11 TCIEU Bit Underflow Interrupt Enable Enables disables interrupt requests TCImU m 1 2 4 5 7 8 10 11 TTGE Bit A D Conversion Start Request Enable Enables disables generation of A D conversion start requests by ...

Page 481: ...egend x Undefined Bit Symbol Bit Name Description R W b5 to b0 Reserved The read value is undefined The write value should always be 0 R W b6 Reserved This bit is read as 1 and cannot be modified R b7 TCFD Count Direction Flag 0 TPUm TCNT counts down 1 TPUm TCNT counts up m 1 2 4 5 7 8 10 11 R Note Bit 7 in TSR of TPU0 TPU3 unit 0 TPU6 and TPU9 unit 1 is reserved This bit is read as 1 The write va...

Page 482: ...U2 TGRA 0008 8138h TPU2 TGRB 0008 813Ah TPU3 TGRA 0008 8148h TPU3 TGRB 0008 814Ah TPU3 TGRC 0008 814Ch TPU3 TGRD 0008 814Eh TPU4 TGRA 0008 8158h TPU4 TGRB 0008 815Ah TPU5 TGRA 0008 8168h TPU5 TGRB 0008 816Ah TPU6 TGRA 0008 8188h TPU6 TGRB 0008 818Ah TPU6 TGRC 0008 818Ch TPU6 TGRD 0008 818Eh TPU7 TGRA 0008 8198h TPU7 TGRB 0008 819Ah TPU8 TGRA 0008 81A8h TPU8 TGRB 0008 81AAh TPU9 TGRA 0008 81B8h TPU...

Page 483: ...7 b6 Reserved These bits are read as 0 The write value should always be 0 R W TSTRA starts or stops TCNT count operation for TPU0 to TPU5 TSTRB starts or stops TCNT count operation for TPU6 to TPU11 Before setting the operating mode in TPUm TMDR or setting the TPUm TCNT count clock in TPUm TCR stop the TPUm TCNT counter CSTj Bits Counter Start j 0 to 5 These bits start or stop the TCNT counter Whe...

Page 484: ...ization 4 R W b5 SYNC5 Timer Synchronization 5 R W b7 b6 Reserved These bits are read as 0 The write value should always be 0 R W Note To set synchronous operation the SYNCj bit j 0 to 5 for at least two channels must be set to 1 To set synchronous clearing the TCNT clearing source must also be set by the CCLR 2 0 bits in TCR in addition to the SYNCj bit TSYRA selects independent operation or sync...

Page 485: ...ion setting procedure Figure 15 3 shows an example of the count operation setting procedure Operation selection Periodic counter Free run counter Select counter clearing source Select counter clock Set period Start count Start count Select output compare register Periodic counter Free run counter 1 2 3 4 5 Select the counter clock with the TPSC 2 0 bits in TCR At the same time select the input clo...

Page 486: ...e 15 4 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TPUm TGRy for setting the period is set as an output compare register and counter clearing by compare match is selected by the CCLR 2 0 bits in TPUm TCR After the settings have been made TCNT starts count up operation as a ...

Page 487: ...y TIOR The set initial value is output on the TIOCyn pin until the first compare match occurs y A to D n 0 to 11 1 Set the timing for generating a compare match in TGRy 2 Set the CSTj bit in TSTRy to start count operation y A B j 0 to 5 3 Figure 15 6 Example of Setting Procedure for Waveform Output by Compare Match b Examples of waveform output operation Figure 15 7 shows an example of low output ...

Page 488: ...e It is also possible to specify the counter input clock or compare match signal of TPU0 TPU1 TPU3 and TPU4 TPU6 TPU7 TPU9 and TPU10 as the input capture source Note When another channel s counter input clock is used as the input capture input for TPU0 and TPU3 TPU6 and TPU9 PCLK 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if...

Page 489: ...g and falling edges have been selected as the TIOCAn pin input capture input edge the falling edge has been selected as the TIOCBn pin input capture input edge and counter clearing by TPUm TGRB input capture has been set for TPUm TCNT Time Counter cleared by TIOCB input falling edge TCNT value 0160h 0000h TIOCB TIOCA TGRB TGRA 0180h 0005h 0010h 0005h 0160h 0010h 0180h Figure 15 10 Example of Input...

Page 490: ...hronous operation selection Set TCNT Synchronous presetting Synchronous presetting Synchronous clearing Select counter clearing source Counter clearing Start count Set synchronous counter clearing Synchronous clearing Start count Clearing source generation channel No Yes 1 2 3 5 4 5 Set the SYNCj bit in TSYRy corresponding to the channels to be set for synchronous operation to 1 y A B j 0 to 5 1 W...

Page 491: ... set for the TPU1 and TPU2 counter clearing source Three phase PWM waveforms are output from pins TIOCA0 TIOCA1 and TIOCA2 At this time synchronous presetting and synchronous clearing by TPU0 TGRB compare match are performed for TPUm TCNT of TPU0 to TPU2 and the data set in TPU0 TGRB is used as the PWM cycle For details on PWM modes see section 15 3 5 PWM Modes Time 0000h TIOCA0 TIOCA1 TIOCA2 TPU0...

Page 492: ...ion Table 15 23 Register Combinations in Buffer Operation Unit Channel Timer General Register Buffer Register 0 TPU0 TPU0 TGRA TPU0 TGRC TPU0 TGRB TPU0 TGRD TPU3 TPU3 TGRA TPU3 TGRC TPU3 TGRB TPU3 TGRD 1 TPU6 TPU6 TGRA TPU6 TGRC TPU6 TGRB TPU6 TGRD TPU9 TPU9 TGRA TPU9 TGRC TPU9 TGRB TPU9 TGRD When TPUm TGRy is an output compare register When a compare match occurs the value in the buffer register ...

Page 493: ...r TCNT Timer general register Figure 15 14 Input Capture Buffer Operation 1 Example of Buffer Operation Setting Procedure Figure 15 15 shows an example of the buffer operation setting procedure Select TGRm function Buffer operation Set buffer operation Start count Buffer operation 1 2 3 Set TGRy as an input capture register or output compare register by TIOR y A to D 1 Set TGRy for buffer operatio...

Page 494: ... example are TPU0 TCNT clearing by compare match B high output at compare match A and low output at compare match B As buffer operation has been set when compare match A occurs the output changes and the TPU0 TGRC value is simultaneously transferred to TPU0 TGRA This operation is repeated each time compare match A occurs For details on PWM modes see section 15 3 5 PWM Modes TCNT value TPU0 TGRB 00...

Page 495: ...register and TPUm TGRC Counter clearing by TGRA input capture has been set for TPUm TCNT and both rising and falling edges have been selected as the TIOCAn pin input capture input edge As buffer operation has been set when the TCNT value is stored in TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC Time 0532h 0F07h 0532h 0F07h 09FBh ...

Page 496: ...the register combinations used in cascaded operation Note When phase counting mode is set for TPU1 or TPU4 TPU7 or TPU10 the counter clock setting is invalid and the counter operates independently in phase counting mode Table 15 24 Cascaded Combinations Unit Combination Upper 16 Bits Lower 16 Bits 0 TPU1 and TPU 2 TPU1 TCNT TPU2 TCNT TPU 4 and TPU 5 TPU4 TCNT TPU5 TCNT 1 TPU 7 and TPU 8 TPU7 TCNT ...

Page 497: ...pper 16 bits of the 32 bit data are transferred to TPU1 TGRA and the lower 16 bits to TPU2 TGRA TPU2 TCNT clock TPU2 TCNT FFFFh 0000h 0001h TIOCA1 TIOCA2 TPU1 TGRA 03A2h TPU2 TGRA 0000h TPU1 TCNT clock TPU1 TCNT 03A1h 03A2h Figure 15 19 Example of Cascaded Operation 1 Figure 15 20 shows the operation when counting upon TPU2 TCNT overflow underflow has been set for TPU1 TCNT and phase counting mode...

Page 498: ... and TIOCCn pins at compare matches A and C respectively The outputs specified by the IOB 3 0 bits in TPUm TIOR H and IOD 3 0 bits in TPUm TIORL are output from the TIOCAn and TIOCCn pins at compare matches B and D respectively The initial output value is the value set in TGRA or TGRC If the set values of paired TGRy registers are identical the output value does not change even when a compare matc...

Page 499: ...CB2 TPU 3 TPU3 TGRA TIOCA3 TIOCA3 TPU3 TGRB TIOCB3 TPU3 TGRC TIOCC3 TIOCC3 TPU3 TGRD TIOCD3 TPU 4 TPU4 TGRA TIOCA4 TIOCA4 TPU4 TGRB TIOCB4 TPU 5 TPU5 TGRA TIOCA5 TIOCA5 TPU5 TGRB TIOCB5 1 TPU 6 TPU6 TGRA TIOCA6 TIOCA6 TPU6 TGRB TIOCB6 TPU6 TGRC TIOCC6 TIOCC6 TPU6 TGRD TIOCD6 TPU 7 TPU7 TGRA TIOCA7 TIOCA7 TPU7 TGRB TIOCB7 TPU 8 TPU8 TGRA TIOCA8 TIOCA8 TPU8 TGRB TIOCB8 TPU 9 TPU9 TGRA TIOCA9 TIOCA9 ...

Page 500: ...clock with the TPSC 2 0 bits in TCR At the same time select the input clock edge with the CKEG 1 0 bits in TCR 1 Select the TGRy register to be used as the TCNT clearing source with the CCLR 2 0 bits in TCR y A to D 2 Set TGRy as an output compare register by TIOR and select the initial value and output value 3 Set the cycle in TGRy selected in 2 and set the duty in the other TGRy registers 4 Sele...

Page 501: ...IOCA Figure 15 22 Example of PWM Mode Operation 1 Figure 15 23 shows an example of PWM mode 2 operation In this example synchronous operation is specified for TPU0 and TPU1 TPU1 TGRB compare match is set as the TPUm TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TPUm TGRy registers TPU0 TGRA to TPU0 TGRD and TPU1 TGRA to output a 5 phase PWM ...

Page 502: ...put does not change when compare matches in cycle register and duty register occur simultaneously TGRA 0000h TIOCA TGRB TGRB changed TCNT value TCNT value TCNT value TGRB changed TGRB changed TGRB changed 0 duty cycle 100 duty cycle Time Time TGRB changed 0 duty cycle Output does not change when compare matches in cycle register and duty register occur simultaneously TGRB changed TGRB changed TGRB...

Page 503: ... interrupt request is generated when an underflow occurs while TCNT is counting down a TCIU interrupt request is generated The TCFD bit in TPUm TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 15 26 shows the correspondence between external clock pins and channels Table 15 26 Clock Input Pins in Phase Counting Mode Unit Chann...

Page 504: ...15 26 shows an example of phase counting mode 1 operation and table 15 27 lists the TCNTn up down count conditions TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 TCNT value Up count Down count Time Figure 15 26 Example of Phase Counting Mode 1 Operation Table 15 27 Up Down Count Conditions in Phase Counting Mode 1 TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 Ope...

Page 505: ...TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 TCNT value Up count Down count Time Figure 15 27 Example of Phase Counting Mode 2 Operation Table 15 28 Up Down Count Conditions in Phase Counting Mode 2 TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care Hig...

Page 506: ...TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 TCNT value Up count Down count Time Figure 15 28 Example of Phase Counting Mode 3 Operation Table 15 29 Up Down Count Conditions in Phase Counting Mode 3 TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care Hig...

Page 507: ...TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 TCNT value Time Down count Up count Figure 15 29 Example of Phase Counting Mode 4 Operation Table 15 30 Up Down Count Conditions in Phase Counting Mode 4 TCLKA TPU1 TPU5 TCLKC TPU2 TPU4 TCLKB TPU1 TPU5 TCLKD TPU2 TPU4 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don...

Page 508: ...n control cycle TPU0 TGRB is used for input capture with TPU0 TGRB and TPU0 TGRD operating in buffer mode The TPU1 counter input clock is specified as the TPU0 TGRB input capture source and the pulse width of 2 phase encoder 4 multiplication pulses is detected TPU1 TGRA and TPU1 TGRB for TPU1 are specified for input capture TPU0 TGRA and TPU0 TGRC compare matches are selected as the input capture ...

Page 509: ...pt Sources There are three kinds of TPU interrupt sources TPUm TGRy input capture compare match TPUm TCNT overflow and TPUm TCNT underflow Relative channel priority levels can be changed by the interrupt controller but the priority within a channel is fixed For details see section 10 Interrupt Control Unit ICU ...

Page 510: ... Possible Not possible TGI3D TPU3 TGRD input capture compare match Possible Not possible TCI3V TPU3 TCNT overflow Not poss ble Not possible TPU4 TGI4A TPU4 TGRA input capture compare match Possible Possible TGI4B TPU4 TGRB input capture compare match Possible Not possible TCI4V TPU4 TCNT overflow Not poss ble Not possible TCI4U TPU4 TCNT underflow Not poss ble Not possible TPU5 TGI5A TPU5 TGRA inp...

Page 511: ...ss ble Not possible TCI11U TPU11 TCNT underflow Not poss ble Not possible Note This table shows the initial state immediately after a reset The relative channel priority levels can be changed by the interrupt controller 1 Input Capture Compare Match Interrupt An interrupt is requested when the TGIEy bit y A B C D in TPUm TIER is set to 1 by the occurrence of a TPUm TGRy input capture compare match...

Page 512: ...DMAC activation sources one for each channel 15 7 A D Converter Activation The TPU can activate the A D converter by the TPUm TGRA input capture compare match for each channel Moreover the A D converter is activated by the TGRA to TGRD input capture compare match from TPU0 When the TTGE bit in TPUm TIER is set to 1 the TPU requests the A D converter to start A D conversion by the occurrence of a T...

Page 513: ...unt timing in internal clock operation and figure 15 32 shows TCNT count timing in external clock operation Falling edge Rising edge Falling edge Internal clock TCNT TCNT input clock PCLK N 1 N N 2 N 1 Figure 15 31 Count Timing in Internal Clock Operation Falling edge Rising edge Falling edge External clock TCNT TCNT input clock PCLK N 1 N N 2 N 1 Figure 15 32 Count Timing in External Clock Operat...

Page 514: ... or TPUm TIOR is output to the output compare output pin TIOCyn y A to D n 0 to 11 After a match between TCNT and TGRy the compare match signal is not generated until the TCNT input clock is generated Figure 15 33 shows output compare output timing N TCNT input clock Compare match signal TPUm TCNT TPUm TGRy PCLK N 1 TIOCyn pin N Figure 15 33 Output Compare Output Timing 3 Input Capture Signal Timi...

Page 515: ...er clearing by compare match occurrence is specified and figure 15 36 shows the timing when counter clearing by input capture occurrence is specified 0000h N Compare match signal Counter clear signal TPUm TCNT TPUm TGRy PCLK N Figure 15 35 Counter Clear Timing Compare Match 0000h N Input capture signal Counter clear signal TPUm TCNT TPUm TGRy PCLK N Figure 15 36 Counter Clear Timing Input Capture ...

Page 516: ...eration Timing Figures 15 37 and 15 38 show the timings in buffer operation Compare match signal TGRA TGRB TCNT PCLK TGRC TGRD N N 1 n n N Figure 15 37 Buffer Operation Timing Compare Match Input capture signal TGRA TGRB TCNT PCLK TGRC TGRD N N 1 N N 1 n n N Figure 15 38 Buffer Operation Timing Input Capture ...

Page 517: ...CLK Compare match signal N N N 1 Note For the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU Figure 15 39 TGImy Interrupt Timing Compare Match 2 Interrupt Flag Setting to 1 in Case of Input Capture Figure 15 40 shows the timing for setting the interrupt flag by input capture occurrence N Input capture signal TGRy TCNT PCLK N Note For the corresponding interrupt vec...

Page 518: ...currence TCNT input clock TCNT overflow Overflow signal PCLK FFFFh 0000h Note For the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU Interrupt flag IR flag in IRi of ICU i interrupt vector number Figure 15 41 TCImV Interrupt Setting Timing TCNT input clock TCNT underflow Underflow signal PCLK FFFFh 0000h Note For the corresponding interrupt vector number see sectio...

Page 519: ...states in the case of single edge detection and at least 2 5 states in the case of both edge detection The TPU will not operate properly with a narrower pulse width In phase counting mode the phase difference and overlap between the two input clocks must be at least 1 5 states and the pulse width must be at least 2 5 states Figure 15 43 shows the input clock conditions in phase counting mode Overl...

Page 520: ...en TPUm TCNT Write and Clear Operations If the counter clearing signal is generated in a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 15 44 shows the timing in this case N 0000h TCNT PCLK Counter clear signal TCNT write by CPU Figure 15 44 Conflict between TPUm TCNT Write and Clear Operations 15 9 5 Conflict between TPUm TCNT Write and Increment Operat...

Page 521: ... this case TCNT TGRy PCLK Compare match signal M N TGR write by CPU Disabled N 1 TGRm write data N Figure 15 46 Conflict between TPUm TGRy Write and Compare Match 15 9 7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in a TPUm TGRy write cycle the data transferred to TGRy by the buffer operation will be the data before writing Figure 15 47 shows the timing in th...

Page 522: ...s case Internal data bus TGRy PCLK Input capture signal Buffer register read by CPU M N N Figure 15 48 Conflict between TPUm TGRy Read and Input Capture 15 9 9 Conflict between TPUm TGRy Write and Input Capture If the input capture signal is generated in a TGRy write cycle the input capture operation takes precedence and the write to TGRy is not performed Figure 15 49 shows the timing in this case...

Page 523: ...11 Conflict between Overflow Underflow and Counter Clearing If overflow underflow and counter clearing occur simultaneously TPUm TCNT counter is cleared with the generation of the compare match interrupt and an overflow interrupt is generated Figure 15 51 shows the operation timing when a TPUm TGRy compare match is specified as the clearing source and FFFFh is set in TGRy FFFFh TCNT input clock Co...

Page 524: ...ite data TCNT write by CPU Interrupt flag IR flag in IRi of ICU i interrupt vector number Note For the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU Figure 15 52 Conflict between TPUm TCNT Write and Overflow 15 9 13 Multiplexing of I O Pins In the RX610 Group the TCLKA A input pin is multiplexed with the TIOCC0 I O pin the TCLKB A input pin with the TIOCD0 I O pin...

Page 525: ... Item Specifications Number of output bits Up to 32 bits Pulse output Two units each capable of output through four pin groups Output trigger signals are selectable Non overlapping operation is possible Inverted output is selectable Output data transfer Can operate together with the DTC and DMAC When TPU interrupt is in use Power down function Module stop state can be set for each unit Table 16 2 ...

Page 526: ...ODRL NDRL Control logic NDERH PMR NDERL PCR Internal data bus NDRH NDRL PODRH PODRL NDRH Pulse output pins group 3 Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Figure 16 ...

Page 527: ...24 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 Pulse output pins group 7 Pulse output pins group 6 Pulse output pins group 5 Pulse output pins group 4 NDRH NDRL PTRSLR I n t e r n a l d a t a b u s PPG output mode register PPG output control register Next data enable register H Next data enable register L PPG trigger select register Next data register H Next data register L Output data register H Outp...

Page 528: ...ut PO4 Output Group 1 pulse output PO5 Output PO6 Output PO7 Output PO8 Output Group 2 pulse output PO9 Output PO10 Output PO11 Output PO12 Output Group 3 pulse output PO13 Output PO14 Output PO15 Output PPG1 PO16 Output Group 4 pulse output PO17 Output PO18 Output PO19 Output PO20 Output Group 5 pulse output PO21 Output PO22 Output PO23 Output PO24 Output Group 6 pulse output PO25 Output PO26 Out...

Page 529: ...er L PODRL 00h 0008 81FBh 8 Next data register H NDRH 00h 0008 81FCh 3 8 Next data register L NDRL 00h 0008 81FDh 4 8 Next data register H NDRH 00h 0008 81FEh 3 8 Next data register L NDRL 00h 0008 81FFh 4 8 Notes 1 When pulse output groups 2 and 3 have the same output trigger by PPG0 PCR settings the PPG0 NDRH address is 0008 81ECh When they have different output triggers the PPG0 NDRH addresses ...

Page 530: ...ls PTRSL Bit PPG Trigger Select This bit selects either TPU0 to TPU3 or TPU6 to TPU9 as a set of trigger channels for PPG1 When this bit is set to 0 TPU0 to TPU3 are selected as a set of trigger channels for PPG1 When it is set to 1 TPU6 to TPU9 are selected as a set of trigger channels for PPG1 PPG unit 0 compare match input PPG unit 1 compare match input PTRSLR PTRSL TPU PPG Compare match input ...

Page 531: ... 0 Data transfer is disabled 1 Data transfer is enabled R W b1 NDER9 Next Data Transfer Enable R W b2 NDER10 Next Data Transfer Enable R W b3 NDER11 Next Data Transfer Enable R W b4 NDER12 Next Data Transfer Enable R W b5 NDER13 Next Data Transfer Enable R W b6 NDER14 Next Data Transfer Enable R W b7 NDER15 Next Data Transfer Enable R W PPG0 NDERH selects the pins PO8 to PO15 for outputs of pulse ...

Page 532: ...fer Enable R W b4 NDER4 Next Data Transfer Enable R W b5 NDER5 Next Data Transfer Enable R W b6 NDER6 Next Data Transfer Enable R W b7 NDER7 Next Data Transfer Enable R W PPG0 NDERL selects the pins PO0 to PO7 for outputs of pulse from the PPG on a bit by bit basis NDERj Bits Next Data Transfer Enable j 0 to 7 When these bits are set to 1 the output trigger specified by PTRSLR transfers data from ...

Page 533: ...abled 1 Data transfer is enabled R W b1 NDER25 Next Data Transfer Enable R W b2 NDER26 Next Data Transfer Enable R W b3 NDER27 Next Data Transfer Enable R W b4 NDER28 Next Data Transfer Enable R W b5 NDER29 Next Data Transfer Enable R W b6 NDER30 Next Data Transfer Enable R W b7 NDER31 Next Data Transfer Enable R W PPG1 NDERH selects the pins PO24 to PO31 for outputs of pulse from the PPG on a bit...

Page 534: ...r Enable R W b4 NDER20 Next Data Transfer Enable R W b5 NDER21 Next Data Transfer Enable R W b6 NDER22 Next Data Transfer Enable R W b7 NDER23 Next Data Transfer Enable R W PPG1 NDERL selects the pins PO16 to PO23 for outputs of pulse from the PPG on a bit by bit basis NDERj Bits Next Data Transfer Enable j 16 to 23 When these bits are set to 1 the output trigger specified by PTRSLR transfers data...

Page 535: ...t Data Register R W b5 POD13 Output Data Register R W b6 POD14 Output Data Register R W b7 POD15 Output Data Register R W PPG0 PODRH stores pulse output values For bits corresponding to pins that have been set for pulse output by PPG0 NDERH the output trigger transfers the values in PPG0 NDRH to this register PPG0 PODRL Bit Symbol Bit Name Description R W b0 POD0 Output Data Register For bits corr...

Page 536: ...POD29 Output Data Register R W b6 POD30 Output Data Register R W b7 POD31 Output Data Register R W PPG1 PODRH stores pulse output values For bits corresponding to pins that have been set for pulse output by PPG1 NDERH the output trigger transfers the values in PPG1 NDRH to this register PPG1 PODRL Bit Symbol Bit Name Description R W b0 POD16 Output Data Register For bits corresponding to pins that...

Page 537: ...e 0008 81ECh Bit Symbol Bit Name Description R W b0 NDR8 Next Data Register The output trigger specified by PPG0 PCR transfers the values in this register to the corresponding bits in PPG0 PODRH R W b1 NDR9 Next Data Register R W b2 NDR10 Next Data Register R W b3 NDR11 Next Data Register R W b4 NDR12 Next Data Register R W b5 NDR13 Next Data Register R W b6 NDR14 Next Data Register R W b7 NDR15 N...

Page 538: ...ess and can be accessed at one time 0008 81EDh Bit Symbol Bit Name Description R W b0 NDR0 Next Data Register The output trigger specified by PPG0 PCR transfers the values in this register to the corresponding bits in PPG0 PODRL R W b1 NDR1 Next Data Register R W b2 NDR2 Next Data Register R W b3 NDR3 Next Data Register R W b4 NDR4 Next Data Register R W b5 NDR5 Next Data Register R W b6 NDR6 Next...

Page 539: ...fter reset 0 0 0 0 0 0 0 0 NDR23 NDR22 NDR21 NDR20 NDR19 NDR18 NDR17 NDR16 PPG1 NDRH PPG1 NDRL PPG1 NDRH PPG1 NDRH stores the next data for pulse output The PPG1 NDRH address differs depending on whether pulse output groups have the same output trigger or different output triggers 1 When pulse output groups 6 and 7 have the same output trigger If pulse output groups 6 and 7 have the same output tr...

Page 540: ...es in this register to the corresponding bits in PPG1 PODRH R W b1 NDR25 Next Data Register R W b2 NDR26 Next Data Register R W b3 NDR27 Next Data Register R W b7 to b4 Reserved These bits are always read as 1 The write value should always be 1 R W PPG1 NDRL PPG1 NDRL stores the next data for pulse output The PPG1 NDRL address differs depending on whether pulse output groups have the same output t...

Page 541: ... W b4 NDR20 Next Data Register The output trigger specified by PPG1 PCR transfers the values in this register to the corresponding bits in PPG1 PODRL R W b5 NDR21 Next Data Register R W b6 NDR22 Next Data Register R W b7 NDR23 Next Data Register R W Pulse output group 4 0008 81FFh Bit Symbol Bit Name Description R W b0 NDR16 Next Data Register The output trigger specified by PPG1 PCR transfers the...

Page 542: ... in TPU1 1 0 Compare match in TPU2 1 1 Compare match in TPU3 R W b5 b4 G2CMS 1 0 Group 2 Compare Match Select b5 b4 0 0 Compare match in TPU0 0 1 Compare match in TPU1 1 0 Compare match in TPU2 1 1 Compare match in TPU3 R W b7 b6 G3CMS 1 0 Group 3 Compare Match Select b7 b6 0 0 Compare match in TPU0 0 1 Compare match in TPU1 1 0 Compare match in TPU2 1 1 Compare match in TPU3 R W PPG1 PCR Bit Symb...

Page 543: ...ompare match in TPU2 1 1 Compare match in TPU3 When the PTRSL bit in PPG1 PTRSLR is set to 1 b5 b4 0 0 Compare match in TPU6 0 1 Compare match in TPU7 1 0 Compare match in TPU8 1 1 Compare match in TPU9 R W b7 b6 G3CMS 1 0 Group 7 Compare Match Select When the PTRSL bit in PPG1 PTRSLR is set to 0 b7 b6 0 0 Compare match in TPU0 0 1 Compare match in TPU1 1 0 Compare match in TPU2 1 1 Compare match ...

Page 544: ...d TPUm 1 Non overlapping operation Output values updated on compare match A or B in the selected TPUm m 0 to 3 R W b2 G2NOV Group 2 Non Overlap 0 Normal operation Output values updated on compare match A in the selected TPUm 1 Non overlapping operation Output values updated on compare match A or B in the selected TPUm m 0 to 3 R W b3 G3NOV Group 3 Non Overlap 0 Normal operation Output values updat...

Page 545: ...Group 7 Non Overlap 0 Normal operation Output values updated on compare match A in the selected TPUm 1 Non overlapping operation Output values updated on compare match A or B in the selected TPUm m 0 to 3 6 to 9 R W b4 G0INV Group 4 Output Polarity Invert 0 Inverted output 1 Direct output R W b5 G1INV Group 5 Output Polarity Invert 0 Inverted output 1 Direct output R W b6 G2INV Group 6 Output Pola...

Page 546: ...546 of 1006 Feb 20 2013 GjNOV Bits Group k Non Overlap j 0 to 3 k 0 to 7 Each bit selects normal operation or non overlapping operation for pulse output group j GjINV Bits Group k Invert j 0 to 3 k 0 to 7 Each bit selects direct output or inverted output for pulse output group k ...

Page 547: ...l settings in the corresponding PPGm PODRH and PPGm PODRL When the compare match event selected in PPGm PCR occurs the output values are updated by transfer of the values in the corresponding PPGm NDRH and PPGm NDRL to PPGm PODRH and PPGm PODRL respectively Consecutive output of up to 16 bits of data is possible by writing new output data to PPGm NDRH and PPGm NDRL before the next compare match Ou...

Page 548: ...RH and PPGm NDRL m 0 1 are transferred to PPGm PODRH and PPGm PODRL respectively and then output on the corresponding pins Figure 16 5 shows the timing of the above operation In this case the timing when compare match A triggers normal output from groups 2 and 3 is shown TCNT N N 1 PCLK TGRA N Compare match A signal NDRH m n PODRH PO8 to PO15 n m n Figure 16 5 Timing of Transfer and Output of the ...

Page 549: ...he TPU unit 0 to make TGRA an output compare register output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with the TPSC 2 0 bits in TCR Select the counter clear source with the CCLR 2 0 bits 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the bits for the pins to be used f...

Page 550: ... set TIOR of the TPU to make TGRA an output compare register toggle output 2 Set the PPG output trigger period 3 Select the counter clock source with the TPSC 2 0 bits in TCR Select the counter clear source with the CCLR 2 0 bits 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the bits for the pins to be u...

Page 551: ...so that the counter will be cleared by compare match A Set the TGIEA bit in TPUm TIER to 1 to enable the compare match input capture A TGImA interrupt 2 Write F8h to PPG0 NDERH and set the G3CMS 1 0 and G2CMS 1 0 bits in PPG0 PCR to select the respective compare matches in the TPUm selected in the previous step to be the output triggers Write output data 80h to PPG0 NDRH 3 The timer counter in the...

Page 552: ...ut operation Compare match B Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D Compare match A Figure 16 9 Non Overlapping Pulse Output Therefore compare match B before compare match A allows 0 valued data to be transferred in advance of 1 valued data Do not change the values in PPGm NDRH and PPGm NDRL during the interval from compare match B to compare mat...

Page 553: ...0 2013 Do not write to NDR here NDR PODR Compare match B Compare match A Write to NDR here Low output Low High output Write to NDR Write to NDR Low output Low High output Write to NDR here Do not write to NDR here Figure 16 10 Non Overlapping Operation and Write Timing to PPGm NDRH and PPGm NDRL ...

Page 554: ...e pulse output trigger period in TGRB and the non overlap period in TGRA 3 Select the counter clock source with the TPSC 2 0 bits in TCR Select the counter clear source with the CCLR 2 0 bits 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the bits for the pins to be used for pulse output to 1 7 Select the...

Page 555: ...put compare registers toggle output 2 Set the pulse output trigger period in TGRB and the non overlap period in TGRA 3 Select the counter clock source with the TPSC 2 0 bits in TCR Select the counter clear source with the CCLR 2 0 bits 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the bits for the pins t...

Page 556: ...put Figure 16 13 shows an example in which pulse output from the PPG0 is used for four phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA 0000h NDRH PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non overlap margin 00 95 05 65 41 59 50 56 14 95 05 65 56 95 65 65 59 95 Figure 16 13 Example of Non Overlapping Pulse Output Example of Four Phase Complementary Non Overlapping ...

Page 557: ...matches in the TPUm selected in the previous step to be the output triggers Set the G3NOV and G2NOV bits in PPG0 PMR to 1 to select non overlapping outputs Write output data 95h in PPG0 NDRH 3 The timer counter in the TPUm starts When a compare match with TGRB occurs outputs change from high to low When a compare match with TGRA occurs outputs change from low to high the change from low to high is...

Page 558: ...the values that are the inverse of the respective values in PPG0 PODRH and PPG0 PODRL can be output Figure 16 14 shows the outputs when the G3INV and G2INV bits are cleared to 0 in addition to the settings in figure 16 13 TCNT value TCNT TGRB TGRA 0000h NDRH 00 95 05 65 41 59 50 56 14 95 05 65 PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time 56 95 65 65 59 95 Figure 16 14 Inverted Pulse Output Exa...

Page 559: ...0 input capture as well as by compare match When a TPUm TGRA m 0 to 3 functions as an input capture register in the TPU unit 0 channel selected by PPG0 PCR pulse output is triggered by the input capture signal Figure 16 15 shows the timing of pulse output triggered by input capture PCLK N M N TIOC pin Input capture signal NDR PODR M N PO Figure 16 15 Timing of Pulse Output Triggered by Input Captu...

Page 560: ... 16 4 Usage Note 16 4 1 Module Stop Function Setting Operation of the PPG can be disabled or enabled by the module stop control register The initial setting is for operation of the PPG to be halted Register access is enabled by clearing module stop state For details see section 8 Low Power Consumption ...

Page 561: ... PCLK 8192 External clock Number of channels 8 bits x 2 channels x 2 units Compare match 8 bit mode compare match A compare match B 16 bit mode compare match A compare match B Counter clear Selected by compare match A or B or an external reset signal Timer output Output pulses with a desired duty cycle or PWM output Cascading of two channels 16 bit count mode 16 bit timer using TMR0 for the upper ...

Page 562: ...CR TCCR TCCR TCORA TCORA PCLK 8 PCLK 2 PCLK 32 PCLK 64 PCLK 1024 PCLK 8192 Counter clock 1 Counter clock 0 Channel 0 TMR0 Channel 1 TMR1 CMIA0 CMIA1 CMIB0 CMIB1 OVI0 OVI1 Control logic TMCI0 TMCI1 TMO0 TMO1 TMRI0 TMRI1 TCORA TCNT TCR TCSR TCORB TCCR Time constant register A Timer counter Timer control register Time constant register B Timer control status register Timer counter control register In...

Page 563: ... 2 Channel 2 TMR2 CMIA2 CMIA3 CMIB2 CMIB3 OVI2 OVI3 Control logic TMCI2 TMCI3 TMO2 TMO3 TMRI2 TMRI3 TCORA TCNT TCR TCSR TCORB TCCR Time constant register A Timer counter Timer control register Time constant register B Timer control status register Timer counter control register Internal clock Note For he corresponding A D converter channels see sec ion 23 A D Converter PCLK 8 PCLK 2 PCLK 32 PCLK 6...

Page 564: ...uts external clock for counter TMRI0 Input Inputs external reset to counter TMR1 TMO1 Output Outputs compare match TMCI1 Input Inputs external clock for counter TMRI1 Input Inputs external reset to counter 1 TMR2 TMO2 Output Outputs compare match TMCI2 Input Inputs external clock for counter TMRI2 Input Inputs external reset to counter TMR3 TMO3 Output Outputs compare match TMCI3 Input Inputs exte...

Page 565: ...or 16 Time constant register A TCORA FFh 0008 8214h 8 or 16 Time constant register B TCORB FFh 0008 8216h 8 or 16 Timer control register TCR 00h 0008 8210h 8 Timer counter control register TCCR 00h 0008 821Ah 8 or 16 Timer control status register TCSR x0h 0008 8212h 8 TMR3 Timer counter TCNT 00h 0008 8219h 8 or 16 Time constant register A TCORA FFh 0008 8215h 8 or 16 Time constant register B TCORB...

Page 566: ...Fh to 00h the interrupt flag is set to 1 For details on the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU and table 17 6 TMR Interrupt Sources 17 2 2 Time Constant Register A TCORA Value after reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b4 b7 b0 b7 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b6 b5 TMR0 TCORA TMR2 TCORA TMR1 TCORA TMR3 TCORA Addresses TMR0 TCORA 0008 8204h TMR1 TCORA ...

Page 567: ...008 8217h TCORB is an 8 bit readable writable register TMR0 TCORB and TMR1 TCORB TMR2 TCORB and TMR3 TCORB comprise a single 16 bit register so they can be accessed together by a word transfer instruction The value in TCORB is continually compared with the value in TCNT When a match is detected the corresponding compare match B signal is set to high Note however that comparison is not performed du...

Page 568: ... 0 Compare match A interrupt requests CMIAm are disabled 1 Compare match A interrupt requests CMIAm are enabled R W b7 CMIEB Compare Match Interrupt Enable B 0 Compare match B interrupt requests CMIBm are disabled 1 Compare match B interrupt requests CMIBm are enabled R W Note To use an external reset set the Pn DDR Bi bit for the corresponding pin to 0 and the Pn ICR Bi bit to 1 TCR specifies the...

Page 569: ...0 R W b7 TMRIS Timer Reset Detection Condition Select 0 Cleared at rising edge of the external reset 1 Cleared when the external reset is high R W Note To use an external clock set the Pn DDR Bi bit for the corresponding pin to 0 and the PnICR Bi bit to 1 For details see section 14 I O Ports TCCR selects an internal clock source for TCNT and the condition for detecting external reset CKS 2 0 Bits ...

Page 570: ...signal 2 TMR1 TMR3 0 0 0 0 Clock input prohibited 1 Uses external clock Counts at rising edge 1 1 0 Uses external clock Counts at falling edge 1 1 Uses external clock Counts at both rising and falling edges 1 0 1 0 0 0 Uses internal clock Counts at PCLK 1 Uses internal clock Counts at PCLK 2 1 0 Uses internal clock Counts at PCLK 8 1 Uses internal clock Counts at PCLK 32 1 0 0 Uses internal clock ...

Page 571: ...are match A occurs 1 1 Output is inverted when compare match A occurs toggle output R W b3 b2 OSB 1 0 Output Select B 1 b3 b2 0 0 No change when compare match B occurs 0 1 Low is output when compare match B occurs 1 0 High is output when compare match B occurs 1 1 Output is inverted when compare match B occurs toggle output R W b4 ADTE A D Trigger Enable 2 0 A D converter start requests by compare...

Page 572: ... B occurs toggle output R W b4 Reserved These bits are always read as 1 The write value should always be 1 R W b7 to b5 Reserved These bits are always read as an undefined value The write value should always be 1 R W Note Timer output is disabled when the OSB 1 0 and OSA 1 0 bits are all 0 Timer output is 0 until the first compare match occurs after a reset TCSR controls compare match output OSA 1...

Page 573: ...atch of TCORA 2 Set the TCSR OSA 1 0 bits to 10b high output and TCSR OSB 1 0 bits to 01b low output causing the output to change to high at a compare match of TCORA and to low at a compare match of TCORB With these settings the 8 bit timer provides pulses output at a cycle determined by TCORA with a pulse width determined by TCORB No software intervention is required The timer output is low until...

Page 574: ...leared when the external reset is high so that TCNT is cleared at the high level input of the TMRIn signal 2 Set the TCSR OSA 1 0 bits to 10b high output and the TCSR OSB 1 0 bits to 01b low output causing the output to change to high at a compare match of TCORA and to low at a compare match of TCORB With these settings the 8 bit timer provides pulses output at a desired delay time from a TMRIn in...

Page 575: ...ck input Note that the external clock pulse width must be at least 1 5 states for increment at a single edge and at least 2 5 states for increment at both edges The counter will not increment correctly if the pulse width is less than these values Internal clock TCNT input clock TCNT PCLK N 1 N N 1 Figure 17 5 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT PCLK...

Page 576: ...h the match is true just before the timer counter is updated Therefore when values of TCORA and TCORB and that of TCNT match the compare match signal is not generated until the next TCNT clock input Figure 17 7 shows this timing For details on the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU and table 17 6 TMR Interrupt Sources Compare match signal TCORy PCLK TCN...

Page 577: ...hows the timing when the timer output is toggled by the compare match A signal Compare match A signal Timer output pin PCLK Figure 17 8 Timing of Timer Output at Compare Match A 17 4 4 Timing of Counter Clear by Compare Match TCNT is cleared when compare match A or B occurs depending on the settings of the TCR CCLR 1 0 bits Figure 17 9 shows the timing of this operation Compare match signal TCNT P...

Page 578: ...e settings of the TCR CCLR 1 0 bits At least 2 states are required from an external reset input to clearing of TCNT Figures 17 10 and 17 11 show the timing of this operation External reset input pin Clear signal TCNT PCLK 2 states 00h N 1 N Figure 17 10 Timing of Clearance by External Reset Rising Edge External reset input pin Clear signal TCNT PCLK 00h N 1 N Figure 17 11 Timing of Clearance by Ex...

Page 579: ...ignal outputted when TCNT overflows changes from FFh to 00h Figure 17 12 shows the timing of this operation For details on the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU and table 17 6 TMR Interrupt Sources TCNT Overflow signal Interrupt flag IRi IR of ICU PCLK i Interrupt vector number 00h FFh Figure 17 12 Timing of Overflow Interrupt Flag Setting ...

Page 580: ...MR0 TCR CCLR 1 0 bits become effective for the 16 bit counter If the TMR0 TCR CCLR 1 0 bits have been set for counter clear at compare match the 16 bit counter TMR0 TCNT and TMR1 TCNT together is cleared when a 16 bit compare match event occurs The 16 bit counter TMR0 TCNT and TMR1 TCNT together is cleared even if counter clear by the TMRI0 pin has been set The settings of the TMR1 TCR CCLR 1 0 bi...

Page 581: ...atch IR178 IR Possible OVI1 TMR1 TCNT overflow IR179 IR Not possible CMIA2 TMR2 TCORA compare match IR180 IR Possible CMIB2 TMR2 TCORB compare match IR181 IR Possible OVI2 TMR2 TCNT overflow IR182 IR Not possible CMIA3 TMR3 TCORA compare match IR183 IR Possible CMIB3 TMR3 TCORB compare match IR184 IR Possible OVI3 TMR3 TCNT overflow IR185 IR Not possible Note For details on the interrupt status fl...

Page 582: ...counter clear TCNT is cleared at the last state in the cycle in which the value of TCNT matches with that of TCORA or TCORB TCNT updates the counter value at this last state Therefore the counter frequency is obtained by the following formula f Counter frequency φ Operating frequency N TCORA and TCORB register setting value f φ N 1 17 7 3 Conflict between TCNT Write and Counter Clear If a counter ...

Page 583: ... TCNT Write and Increment Even if a counting up signal is generated concurrently with CPU write to TCNT the counting up is not performed and the write takes priority as shown in figure 17 14 TCNT input clock TCNT PCLK TCNT write data TCNT write by CPU M N Figure 17 14 Conflict between TCNT Write and Increment ...

Page 584: ...k TCNT TCORy PCLK TCORy write data Not set to high Write to TCORy by CPU Compare match signal y A B N 1 N M N Figure 17 15 Conflict between TCORA or TCORB Write and Compare Match 17 7 6 Conflict between Compare Matches A and B If compare match events A and B occur at the same time the 8 bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare...

Page 585: ...he signal levels of the clocks before and after switching change from low to high as shown in No 2 in table 17 8 the change is considered as an edge Therefore a TCNT clock pulse is generated and TCNT is incremented The erroneous increment of TCNT can also happen when switching between internal and external clocks Table 17 8 Switching of Internal Clocks and TCNT Operation Timing to Change the TCCR ...

Page 586: ...S 2 0 bits changed N 1 N N 2 Notes 1 Includes switching from low to stop and from stop to low 2 Includes switching from stop to high 3 Generated because the change of the signal levels is considered as an edge TCNT is incremented 4 Includes switching from high to stop 17 7 8 Clock Source Setting with Cascaded Connection If 16 bit count mode and compare match count mode are specified at the same ti...

Page 587: ...ations of CMT Item Description Count clock Four internal clocks One clock from PCLK 8 PCLK 32 PCLK 128 and PCLK 512 can be selected individually for each channel Interrupt A compare match interrupt can be requested individually for each channel Power down function Each unit can be placed in a module stop state Control unit Clock selection Module bus CMI0 PCLK 32 PCLK 512 PCLK 128 PCLK 8 Control un...

Page 588: ...timer constant register CMCOR FFFFh 0008 8006h 16 CMT1 Compare match timer control register CMCR 00x0h 0008 8008h 16 Compare match timer counter CMCNT 0000h 0008 800Ah 16 Compare match timer constant register CMCOR FFFFh 0008 800Ch 16 Unit 1 Common Compare match timer start register 1 CMSTR1 0000h 0008 8010h 16 CMT2 Compare match timer control register CMCR 00x0h 0008 8012h 16 Compare match timer ...

Page 589: ...n R W b0 STR0 Count Start 0 0 CMT0 CMCNT count is stopped 1 CMT0 CMCNT count is started R W b1 STR1 Count Start 1 0 CMT1 CMCNT count is stopped 1 CMT1 CMCNT count is started R W b15 to b2 Reserved These bits are always read as 0 The write value should always be 0 R W CMSTR0 selects whether the CMT0 CMCNT or CMT1 CMCNT counter operates or is stopped STR0 Bit Count Start 0 The STR0 bit specifies whe...

Page 590: ...n R W b0 STR2 Count Start 2 0 CMT2 CMCNT count is stopped 1 CMT2 CMCNT count is started R W b1 STR3 Count Start 3 0 CMT3 CMCNT count is stopped 1 CMT3 CMCNT count is started R W b15 to b2 Reserved These bits are always read as 0 The write value should always be 0 R W CMSTR1 selects whether the CMT2 CMCNT or CMT3 CMCNT counter operates or is stopped STR2 Bit Count Start 2 The STR2 bit specifies whe...

Page 591: ...ays be 0 R W b6 CMIE Compare Match Interrupt Enable 0 Compare match interrupt CMIm disabled 1 Compare match interrupt CMIm enabled R W b7 Reserved This bit is always read as an undefined value The write value should always be 1 R W b15 to b8 Reserved These bits are always read as 0 The write value should always be 0 R W CMCR sets the clock used for counting up CKS 1 0 Bits Clock Select These bits ...

Page 592: ...internal clock is selected by bits CKS 1 0 in CMCR and the STRj j 0 to 3 bit in CMSTRy y 0 or 1 is set to 1 CMCNT starts counting up using the selected clock When the value in CMCNT and the value in CMCOR match CMCNT is cleared to 0000h At the same time a compare match interrupt CMIm m 0 to 3 is generated 18 2 5 Compare Match Constant Register CMCOR Addresses CMT0 CMCOR 0008 8006h CMT1 CMCOR 0008 ...

Page 593: ...to 0000h At the same time a compare match interrupt CMIm m 0 to 3 is generated CMCNT then starts counting up again from 0000h Figure 18 2 shows the operation of the CMCNT counter Time Counter cleared by compare match with CMCOR CMCNT value CMCOR 0000h Figure 18 2 CMCNT Counter Operation 18 3 2 CMCNT Count Timing One of four internal clocks PCLK 8 PCLK 32 PCLK 128 and PCLK 512 obtained by dividing ...

Page 594: ...etween CMT1 CMCNT and CMT1 CMCOR IR029 IR Possible Possible CMI2 Compare match between CMT2 CMCNT and CMT2 CMCOR IR030 IR Possible Possible CMI3 Compare match between CMT3 CMCNT and CMT3 CMCOR IR031 IR Possible Possible 18 4 2 Timing of Compare Match Interrupt Generation When CMCNT and CMCOR match a compare match interrupt CMIm m 0 to 3 is generated A compare match signal is generated at the last ...

Page 595: ...T clearing CMCNT has priority over writing to it In this case CMCNT is not written to Figure 18 5 shows the timing to clear the CMCNT counter 0000h N Write to CMCNT CMCNT Compare match signal Internal write signal PCLK Figure 18 5 Conflict between Write and Compare Match Processes of CMCNT 18 5 3 Conflict between Write and Count Up Processes of CMCNT Even when the count up occurs while writing to ...

Page 596: ...ld to be taken while comparing it with the written data 18 5 5 Notes on Compare Match Timer Counter CMCNT and Compare Match Constant Register CMCOR Do not set the CMCNT and the CMCOR to the same value while the count operation of the CMCNT is stopped If the CMCNT and the CMCOR are set to the same value with the CMCNT count operation halted the compare match occurs irrespective of halted count oper...

Page 597: ...er interrupt is generated each time the counter overflows 19 1 Overview Table 19 1 lists the specifications of the WDT Figure 19 1 shows a block diagram of the WDT Table 19 1 Specifications of WDT Item Specifications Count clocks PCLK 4 PCLK 64 PCLK 128 PCLK 512 PCLK 2048 PCLK 8192 PCLK 32768 and PCLK 131072 Number of channels 8 bits x 1 channel Count clear Write to TCNT Operating modes Switchable...

Page 598: ... TCSR Overflow Clock Internal main bus Internal clocks PCLK 512 PCLK 128 PCLK 64 PCLK 4 PCLK 2048 PCLK 131072 PCLK 32768 PCLK 8192 Peripheral bus interface WINB WINA TCSR Timer control status register TCNT Timer counter RSTCSR Reset control status register WINA Write window A register WINB Write window B register Figure 19 1 Block Diagram of WDT Table 19 2 shows the input output pin used for the W...

Page 599: ... status register RSTCSR 1Fh 0008 802Bh 1 8 Write window A register WINA 0008 8028h 2 16 Write window B register WINB 0008 802Ah 2 16 Notes 1 Read only register 2 Write only register 19 2 1 Timer Counter TCNT Address 0008 8029h b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 TCNT is an 8 bit up counter for the internal clock TCNT is initialized to 00h when the TME bit in TCSR is set to 0 ...

Page 600: ...e 0 TCNT stops counting and is initialized to 00h 1 TCNT starts counting R W b6 TMS Timer Mode Select 0 Interval timer mode When TCNT overflows an interval timer interrupt WOVI is requested 1 Watchdog timer mode When TCNT overflows WDTOVF is output R W b7 Reserved This bit is always read as an undefined value The write value should always be 1 R W TCSR selects the clock source to be input to TCNT ...

Page 601: ...verflowed in watchdog timer mode R W Note Only 0 can be written to this bit RSTCSR controls the generation of the internal reset signal when TCNT overflows and selects the type of internal reset signal RSTCSR is initialized to 1Fh by a reset signal from the RES pin or a deep software standby reset but not by the WDT internal reset signal caused by a WDT overflow To read this register use 8 bit acc...

Page 602: ...tween TCNT and TCSR For details see section 19 5 1 Notes on Register Access To write to this register use 16 bit access 19 2 5 Write Window B Register WINB Value after reset Address 0008 802Ah b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5 WINB is a write only register for writing to RSTCSR The writing method varies between writing 0 to the WOVF flag in RSTCSR and writing the RSTE bit in RS...

Page 603: ... as a reset caused by a WDT overflow the RES pin reset has priority and the WOVF flag in RSTCSR is cleared to 0 The WDTOVF signal is output for 257 cycles of PCLK when RSTE 1 and for 256 cycles of PCLK when RSTE 0 The internal reset signal is output for 1027 cycles of PCLK When RSTE 1 an internal reset signal is generated Since the system clock control register SCKCR is initialized the multiplicat...

Page 604: ...generated at intervals TCNT value 00h Time FFh TMS 0 TME 1 WOVI Overflow Overflow Overflow Overflow WOVI An interval timer interrupt request is generated WOVI WOVI WOVI Figure 19 3 Operation in Interval Timer Mode 19 4 Interrupt Source During interval timer mode operation a TCNT overflow generates an interval timer interrupt WOVI For details see section 10 Interrupt Control Unit ICU Table 19 4 WDT...

Page 605: ...fer to TCSR When writing to RSTCSR use a word transfer instruction to the write window B register WINB 0008802Ah The method of writing 0 to the WOVF flag in RSTCSR differs from that of writing to the RSTE bit in RSTCSR To write 0 to the WOVF flag set A5h in the upper byte and 00h in the lower byte and use 16 bit access as shown in figure 19 4 This has no effect on the RSTE bit To write to the RSTE...

Page 606: ...CSR 7 0 Data read from RSTCSR Figure 19 5 Reading from TCNT TCSR and RSTCSR 19 5 2 Conflict between Timer Counter TCNT Write and Increment If a TCNT clock pulse is generated during a TCNT write cycle the write takes priority and the timer counter is not incremented Figure 19 6 shows this operation TCNT input clock TCNT N M Data written to TCNT counter PCLK Writing to TCNT counter by CPU Figure 19 ...

Page 607: ... Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin this LSI will not be initialized correctly Make sure that the WDTOVF signal is not input logically to the RES pin To reset the entire system by means of the WDTOVF signal use a circuit like that shown in figure 19 7 Reset input Reset signal for entire system This LSI RES WDTOVF Figure 19 7 Circuit for System Reset by WDTOVF Signa...

Page 608: ...face Transfer speed Bit rate specifiable with on chip baud rate generator Full duplex communications Transmitter Enables continuous transmission by double buffering Receiver Enables continuous reception by double buffering Input output pins See table 20 3 Data transfer Selectable from LSB first or MSB first transfer Interrupt sources Transmit end transmit data empty receive data full and receive e...

Page 609: ... TEI TXI RXI ERI SCMR SSR SCR SEMR Transmission and reception control BRR RDR TSR RSR Parity error occurrence Legend TDR Module data bus Baud rate generator PCLK 4 PCLK 16 PCLK 64 Clock Parity check RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register SCR Serial control register SSR Serial status register SCMR Smart ca...

Page 610: ...l d a t a b u s PCLK PCLK 4 PCLK 16 PCLK 64 TEI TXI RXI ERI SCMR SSR SCR SMR SEMR BRR TDR TSR RDR RSR TMO1 TMO3 SCKn TMR TMO0 TMO2 RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register SCR Serial control register SSR Serial status register SCMR Smart card mode register BRR Bit rate register SEMR Serial extended mode reg...

Page 611: ...a input TxD1 Output SCI transmit data output SCI2 SCK2 I O SCI2 clock input output RxD2 Input SCI2 receive data input TxD2 Output SCI2 transmit data output SCI3 SCK3 I O SCI3 clock input output RxD3 Input SCI3 receive data input TxD3 Output SCI3 transmit data output SCI4 SCK4 I O SCI4 clock input output RxD4 Input SCI receive data input TxD4 Output SCI4 transmit data output SCI5 SCK5 I O SCI5 cloc...

Page 612: ...I2 Serial mode register SMR 00h 0008 8250h 8 Bit rate register BRR FFh 0008 8251h 8 Serial control register SCR 0xh 0008 8252h 8 Transmit data register TDR FFh 0008 8253h 8 Serial status register SSR 84h 0008 8254h 8 Receive data register RDR 00h 0008 8255h 8 Smart card mode register SCMR F2h 0008 8256h 8 Serial extended mode register SEMR 00h 0008 8257h 8 SCI3 Serial mode register SMR 00h 0008 82...

Page 613: ... register RDR 00h 0008 826Dh 8 Smart card mode register SCMR F2h 0008 826Eh 8 Serial extended mode register SEMR 00h 0008 826Fh 8 SCI6 Serial mode register SMR 00h 0008 8270h 8 Bit rate register BRR FFh 0008 8271h 8 Serial control register SCR 0xh 0008 8272h 8 Transmit data register TDR FFh 0008 8273h 8 Serial status register SSR 84h 0008 8274h 8 Receive data register RDR 00h 0008 8275h 8 Smart ca...

Page 614: ...his way continuous receive operations can be performed Read RDR only once after a receive data full interrupt RXI has occurred Note that if next one frame of data is received before reading receive data from RDR an overrun error occurs RDR cannot be written to by the CPU 20 2 3 Transmit Data Register TDR Addresses SCI0 TDR 0008 8243h SCI1 TDR 0008 824Bh SCI2 TDR 0008 8253h SCI3 TDR 0008 25Bh SCI4 ...

Page 615: ...clock n 2 1 11 PCLK 64 clock n 3 1 R W 4 b2 Reserved This bit is read as 0 The write value should be 0 R W 4 b3 STOP Stop Bit Length Valid only in asynchronous mode 0 1 stop bit 1 2 stop bits R W 4 b4 PM Parity Mode Valid only when the PE bit is 1 in asynchronous mode 0 Selects even parity 1 Selects odd parity R W 4 b5 PE Parity Enable Valid only in asynchronous mode When transmitting 0 Parity bit...

Page 616: ...it Length Selects the stop bit length in transmission In reception only the first stop bit is checked If the second stop bit is 0 it is treated as the start bit of the next transmit frame PM Bit Parity Mode Selects the parity mode even or odd for transmission and reception PE Bit Parity Enable When this bit is set to 1 the parity bit is added to transmit data and the parity bit is checked in recep...

Page 617: ...cycles S 512 2 1 0 0 32 clock cycles S 32 2 Initial value 1 0 1 64 clock cycles S 64 2 1 1 0 372 clock cycles S 372 2 1 1 1 256 clock cycles S 256 2 R W 3 b4 PM Parity Mode Valid only when the PE bit is 1 in asynchronous mode 0 Selects even parity 1 Selects odd parity R W 3 b5 PE Parity Enable Valid only in asynchronous mode When this bit is set to 1 the parity bit is added to transmit data before...

Page 618: ...he parity mode for transmission and reception even or odd For details on the usage of this bit in smart card interface mode see section 20 5 2 Data Format Except in Block Transfer Mode PE Bit Parity Enable Set the PE bit to 1 The parity bit is added to transmit data before transmission and the parity bit is checked in reception BLK Bit Block Transfer Mode Setting this bit to 1 allows block transfe...

Page 619: ...chip baud rate generator The SCKn pin functions as I O port 0 1 On chip baud rate generator The clock with the same frequency as the bit rate is output from the SCKn pin 1 0 External clock The clock with a frequency 16 times the bit rate should be input from the SCKn pin When the SEMR ABCS bit is 1 the clock with a frequency 8 times the bit rate should be input 1 1 External clock The clock with a ...

Page 620: ...b1 b0 0 0 Internal clock The SCKn pin functions as the clock output pin 0 1 Internal clock The SCKn pin functions as the clock output pin 1 0 External clock The SCKn pin functions as the clock input pin 1 1 External clock The SCKn pin functions as the clock input pin R W 1 b2 TEIE Transmit End Interrupt Enable 0 A TEI interrupt request is disabled 1 A TEI interrupt request is enabled R W b3 Reserv...

Page 621: ...eception is halted by clearing the RE bit to 0 the ORER FER and PER flags in SSR are not affected and the previous value is retained TE Bit Transmit Enable Enables or disables serial transmission When this bit is set to 1 serial transmission is started by writing transmit data to TDR Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format RIE Bit ...

Page 622: ...ould be 0 R W b4 RE Receive Enable 0 Serial reception is disabled 1 Serial reception is enabled R W 2 b5 TE Transmit Enable 0 Serial transmission is disabled 1 Serial transmission is enabled R W 2 b6 RIE Receive Interrupt Enable 0 RXI and ERI interrupt requests are disabled 1 RXI and ERI interrupt requests are enabled R W b7 TIE Transmit Interrupt Enable 0 A TXI interrupt request is disabled 1 A T...

Page 623: ... Enables or disables serial transmission When this bit is set to 1 serial transmission is started by writing transmit data to TDR Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format RIE Bit Receive Interrupt Enable Enables or disables RXI and ERI interrupt requests An RXI interrupt request is disabled by clearing the RIE bit to 0 An ERI interr...

Page 624: ...ming Error Flag 0 No framing error occurred 1 A framing error has occurred R W 1 b5 ORER Overrun Error Flag 0 No overrun error occurred 1 An overrun error has occurred R W 1 b6 RDRF Receive Data Full Flag 0 When data is transferred from RDR 1 When data has been received normally and transferred from RSR to RDR R W 2 b7 TDRE Transmit Data Empty Flag 0 When data is transferred to TDR 1 When data is ...

Page 625: ... 1 but the second stop bit is not checked Note that although receive data when the framing error occurs is transferred to RDR no RXI interrupt request occurs In addition when the FER flag is being set to 1 the subsequent serial reception cannot be performed In clock synchronous mode serial transmission also cannot continue Clearing condition When a 0 is written to FER after reading FER 1 After wri...

Page 626: ... RDR has received data Setting condition When data has been received normally and transferred from RSR to RDR Clearing condition When data is transferred from RDR TDRE Bit Transmit Data Empty Flag Indicates whether TDR has data to be transmitted Setting condition When data is transferred from TDR to TSR Clearing condition When data is transferred to TDR ...

Page 627: ... RDR 1 When data has been received normally and transferred from RSR to RDR R W 2 b7 TDRE Transmit Data Empty Flag 0 When data is transferred to TDR 1 When data is transferred from TDR to TSR R W 2 Notes 1 Only 0 can be written to this bit to clear the flag 2 Write 1 when writing is necessary SSR is a register containing status flags of the SCI TEND Flag Transmission End Flag With no error signal ...

Page 628: ... its previous value ERS Flag Error Signal Status Flag Setting condition When a low error signal is sampled Clearing condition When a 0 is written to ERS after reading ERS 1 ORER Flag Overrun Error Flag Indicates that an overrun error has occurred during reception and the reception ends abnormally Setting condition When the next data is received before receive data is read from RDR In RDR the recei...

Page 629: ...CI R01UH0032EJ0120 Rev 1 20 Page 629 of 1006 Feb 20 2013 TDRE Bit Transmit Data Empty Flag Indicates whether TDR has data to be transmitted Setting condition When data is transferred from TDR to TSR Clearing condition When data is transferred to TDR ...

Page 630: ...se bits are read as 1 The write value should be 1 R W b7 BCP2 Base Clock Pulse 2 Selects the number of base clock cycles in combination with the BCP1 and BCP0 bits in SMR Setting values in BCP2 bit in SCMR and BCP1 and BCP0 bits in SMR BCP2 BCP1 BCP0 0 0 0 93 clock cycles S 93 2 0 0 1 128 clock cycles S 128 2 0 1 0 186 clock cycles S 186 2 0 1 1 512 clock cycles S 512 2 1 0 0 32 clock cycles S 32 ...

Page 631: ...31 of 1006 Feb 20 2013 SDIR Bit Bit Order Select Selects the serial parallel conversion format BCP2 Bit Base Clock Pulse 2 Selects the number of base clock cycles in a 1 bit data transfer time in smart card interface mode Set this bit in combination with the BCP1 and BCP2 bits in SMR ...

Page 632: ...ock synchronous mode and smart card interface mode The initial value of BRR is FFh BRR can be read from by the CPU at all times but it can be written to only when the TE and RE bits in SCR are 0 Table 20 5 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous Clock synchronous Smart card interface N ABCS Bit in SEMR 1 Error 1 100 BRR Setting Error 0 1 64 22n 1 B PCLK 106 N 1 32 2...

Page 633: ... asynchronous mode Table 20 7 shows the maximum bit rate settable for each operating frequency Tables 20 9 and 20 11 show sample N settings in BRR in clock synchronous mode and smart card interface mode respectively In smart card interface mode the number of base clock cycles S in a 1 bit data transfer time can be selected For details see section 20 5 4 Receive Data Sampling Timing and Reception M...

Page 634: ... 0 63 0 00 0 64 0 16 0 77 0 16 9600 0 25 0 16 0 31 0 00 0 32 1 36 0 38 0 16 19200 0 12 0 16 0 15 0 00 0 15 1 73 0 19 2 34 31250 0 7 0 00 0 9 1 70 0 9 0 00 0 11 0 00 38400 0 7 0 00 0 7 1 73 0 9 2 34 Bit Rate bps Operating Frequency PCLK MHz 12 288 14 16 n N Error n N Error n N Error 110 2 217 0 08 2 248 0 17 3 70 0 03 150 2 159 0 00 2 181 0 16 2 207 0 16 300 2 79 0 00 2 90 0 16 2 103 0 16 600 1 159...

Page 635: ...4 0 16 19200 0 27 0 00 0 28 1 02 0 31 0 00 0 32 1 36 31250 0 16 1 20 0 17 0 00 0 19 1 70 0 19 0 00 38400 0 13 0 00 0 14 2 34 0 15 0 00 0 15 1 73 Bit Rate bps Operating Frequency PCLK MHz 25 30 33 50 n N Error n N Error n N Error n N Error 110 3 110 0 02 3 132 0 13 3 145 0 33 3 221 0 02 150 3 80 0 47 3 97 0 35 3 106 0 39 3 162 0 15 300 2 162 0 15 2 194 0 16 2 214 0 07 3 80 0 47 600 2 80 0 47 2 97 0...

Page 636: ...External Input Clock MHz Maximum Bit Rate bps 8 2 0000 125000 17 2032 4 3008 268800 9 8304 2 4576 153600 18 4 5000 281250 10 2 5000 156250 19 6608 4 9152 307200 12 3 0000 187500 20 5 0000 312500 12 288 3 0720 192000 25 6 2500 390625 14 3 5000 218750 30 7 5000 468750 16 4 0000 250000 33 8 2500 515625 50 12 500 781250 Note This is an example when the ABCS bit in SEMR is 0 Table 20 8 Maximum Bit Rate...

Page 637: ...124 0 149 0 164 1 61 100k 0 19 0 24 0 39 0 49 0 62 0 74 0 82 0 124 250k 0 7 0 9 0 15 0 19 0 24 0 29 0 32 0 49 500k 0 3 0 4 0 7 0 9 0 14 0 24 1M 0 1 0 3 0 4 2M 0 0 0 1 2 5M 0 0 0 1 0 2 0 4 4M 0 0 5M 0 0 6 25M 0 0 0 1 7 5M 0 0 8 25M 0 0 12 5M 0 0 Legend Space Setting prohibited Can be set but there will be error Note Continuous transmission or reception is not poss ble Table 20 10 Maximum Bit Rate w...

Page 638: ... 14 2848 16 00 18 00 20 00 n N Error n N Error n N Error n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 66 Bit Rate bps Operating Frequency PCLK MHz 25 00 30 00 33 00 50 00 n N Error n N Error n N Error n N Error 9600 0 3 12 49 0 3 5 01 0 4 7 59 0 6 0 01 Table 20 12 Maximum Bit Rate for Each Operating Frequency Smart Card Interface Mode S 372 PCLK MHz Maximum Bit Rate bps n N PCLK MHz Maximum B...

Page 639: ... Selects 16 base clock cycles for 1 bit period 1 Selects 8 base clock cycles for 1 bit period R W b7 to b5 Reserved These bits are read as 0 The write value should be 0 R W Note Writable only when TE in SCR 0 and RE in SCR 0 both serial transmission and reception are disabled SEMR selects the clock source for 1 bit period in asynchronous mode For SCI5 and SCI6 the TMOn output n 0 to 3 of TMR units...

Page 640: ...generate 3 4 clock enable to set an average transfer rate of 3 MHz 16 187 5 kbps Setting examples of TMR and SCI TMR0 TCR 08h TMR0 TCNT is cleared at compare match in TMR0 TCORA the count is incremented at rising edge of PCLK 2 TMR0 TCCR 09h TMR1 TCR 08h TMR1 TCNT is cleared at compare match in TMR1 TCORA the count is incremented at compare match A in TMR0 TCNT TMR1 TCCR 18h TMR0 TCSR 09h Low is o...

Page 641: ...ce state low level recognizes a start bit and starts serial communications Inside the SCI the transmitter and receiver are independent units enabling full duplex communications Both the transmitter and the receiver also have a double buffered structure so that data can be read or written during transmission or reception enabling continuous data transmission and reception 0 Transmit receive data D0...

Page 642: ... can be selected according to the SMR setting Table 20 13 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data S S S P S P S CHR 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 SMR Setting 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Frame Length S P S P STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP 8 bit data 8 bit data 8 bit data 7 bit data 7 bit data 7 bit data ...

Page 643: ...1 Legend M Reception margin N Ratio of bit rate to clock N 16 when ABCS in SEMR 0 N 8 when ABCS in SEMR 1 D Duty cycle of clock D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock frequency deviation Assuming values of F 0 and D 0 5 in formula 1 the reception margin is determined by the formula below M 0 5 1 2 16 100 46 875 However this is only the computed value and a margin of 20 to ...

Page 644: ...mes the bit rate when ABCS in SEMR 0 and 8 times the bit rate when ABCS in SEMR 1 In addition when an external clock is specified the base clock of TMR0 and TMR1 can be selected by the ACS0 bit in SEMR of SCIn n 5 6 When the SCI is operated on an internal clock the clock can be output from the SCKn pin The frequency of the clock output in this case is equal to the bit rate and the phase is such th...

Page 645: ...nput buffer of the corresponding pin is enabled when receiving data or using an external clock 2 Set the clock selection in SCR When the clock output is selected in asynchronous mode the clock is output immediately after SCR settings are made 3 Set the data transfer format in SMR and SCMR 1 4 Write a value corresponding to the bit rate to BRR This step is not necessary if an external clock is used...

Page 646: ...in in the following order start bit transmit data parity bit may be omitted depending on the format and stop bit 4 The SCI checks for updating of writing to the TDR at the time of stop bit output 5 When TDR is updated the next transmit data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the next frame is started 6 If TDR is not updated the TEND flag in SSR is s...

Page 647: ...nuation procedure To continue serial transmission write transmit data to TDR once upon accepting a TXI interrupt request Transmit data can also be written to TDR by initiating the DMAC or DTC 4 Break output at the end of serial transmission To output a break in serial transmission set the Bi bit in DDR of Pn for the port corresponding to the TxDn pin to 1 output port clear the Bi bit in DR of Pn t...

Page 648: ... a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 5 When reception finishes successfully receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Continuous reception is enabled by...

Page 649: ... Accordingly clear the ORER FER and PER bits to 0 before resuming reception Moreover be sure to read the RDR during overrun error processing Figure 20 11 shows samples of flowcharts for serial data reception Table 20 14 SSR Status Flags and Receive Data Handling SSR Status Flag Receive Data Receive Error Type ORER FER PER 1 0 0 Lost Overrun error 0 1 0 Transferred to RDR Framing error 0 0 1 Transf...

Page 650: ...enerated After performing the appropriate error processing be sure to clear the ORER PER and FER flags to 0 Reception cannot be resumed if any of these flags is set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxDn pin 4 Read the receive data in RDR once in the RXI interrupt processing routine 5 Serial reception continuatio...

Page 651: ...ng Parity error processing Yes No Clear ORER FER and PER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER in SSR 1 FER in SSR 1 Break PER in SSR 1 Clear RE bit in SCR to 0 3 Note Read the RDR register End Figure 20 12 Example of Serial Reception Flowchart 2 Asynchronous Mode ...

Page 652: ...r also have a double buffered structure so that the next transmit data can be written during transmission or the previous receive data can be read during reception enabling continuous data transfer Don t care One unit of transfer data character or frame Serial data Synchronization clock LSB MSB Note Holds a high level except during continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Don ...

Page 653: ...nitialization Set data transfer format in SMR and SCMR No Yes Set a value in BRR Clear bits TIE RIE TE RE and TEIE in SCR to 0 Set Bj bit in ICR of Pm to 1 Set TE or RE bit in SCR to 1 and set TIE RIE and TEIE bits in SCR 1 bit interval elapsed Set bits CKE 1 0 in SCR 1 2 3 4 1 When receiving data or using an external clock 2 Set the data transfer format in SMR and SCMR 1 3 Write a value correspon...

Page 654: ... in synchronization with the input clock when use of an external clock has been specified 4 The SCI checks for updating of writing to the TDR at the time of stop bit output 5 When TDR is updated the next transmit data is transferred from TDR to TSR and serial transmission of the next frame is started 6 If TDR is not updated set the SSR flag in TEND to 1 and the TxDn pin retains the output state of...

Page 655: ...ting a TXI interrupt request When transmit data is transferred from TDR to TSR a transmit data empty interrupt TXI request is generated Write transmit data to TDR once upon accepting a transmit data empty interrupt TXI request 3 Serial transmission continuation procedure To continue serial transmission write transmit data to TDR upon accepting a TXI interrupt request Transmit data can also be writ...

Page 656: ...et to 1 at this time an RXI interrupt request is generated Continuous reception is enabled by reading the receive data transferred to RDR in this RXI interrupt processing routine before reception of the next receive data is completed 1 frame RXI interrupt signal SSR ORER flag Serial data Reception clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 7 Bit 6 RDR data read in RXI interrupt processing routine RXI...

Page 657: ...2 3 Receive error processing If a receive error occurs read the ORER flag in SSR perform the relevant error processing and then clear the ORER flag to 0 Data reception cannot be resumed while the ORER flag is set to 1 4 Read the receive data in RDR once upon accepting an RXI interrupt request 5 Serial reception continuation procedure To continue serial reception before the MSB bit 7 of the current...

Page 658: ... switch from transmit mode to simultaneous transmit and receive mode check that the SCI has finished by reading that the TEND flag in SSR in SSR is set to 1 and then initialize the SCR register Then set the TIE RIE TE RE and TEIE bits in SCR to 1 simultaneously by a single instruction To switch from receive mode to simultaneous transmit and receive mode check that the SCI has finished reception an...

Page 659: ...once upon accep ing a TXI interrupt request 3 Receive error processing If a receive error occurs read the ORER flag in SSR perform the relevant error processing and then clear the ORER flag to 0 Data reception cannot be resumed while the ORER flag is set to 1 4 Receive data read Read the receive data in RDR once upon accepting an RXI interrupt request 5 Serial transmission reception con inuation p...

Page 660: ...he figure since this LSI communicates with the IC card using a single transmission line interconnect the TxDn and RxDn pins and pull up the data transmission line to Vcc using a resistor Setting the TE and RE bits in SCR to 1 with the IC card disconnected enables closed transmission reception allowing self diagnosis To supply the IC card with the clock pulses generated by the SCI input the SCKn pi...

Page 661: ...it until the start of the next frame If a parity error is detected during reception a low level error signal is output for 1 etu after 10 5 etu has passed from the start bit If an error signal is sampled during transmission the same data is automatically re transmitted after at least 2 etu Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In normal transmission reception Output from the transmitting station Ds D0 D1 ...

Page 662: ...re is 3Fh When using the inverse convention type write 1 to both the SDIR and SINV bits in SCMR The parity bit is logic level 0 to produce even parity which is prescribed by the smart card standard and corresponds to state Z Since the SNIV bit of this LSI only inverts data bits D7 to D0 write 1 to the PM bit in SMR to invert the parity bit for both transmission and reception Ds A Z Z A A A Z A A A...

Page 663: ... the start bit is sampled with the base clock to perform internal synchronization For data reception the falling edge of the start bit is sampled with the base clock to perform internal synchronization Receive data is sampled on the 16th 32nd 186th 128th 46th 64th 93rd and 256th rising edges of the base clock so that it can be latched at the middle of each bit as shown in figure 20 24 The receptio...

Page 664: ... Feb 20 2013 Internal base clock 372 clock cycles 186 clock cycles D0 D1 185 371 0 371 185 0 0 Receive data RxDn Synchronization sampling timing Data sampling timing Start bit Figure 20 24 Receive Data Sampling Timing in Smart Card Interface Mode When Clock Frequency is 372 Times the Bit Rate ...

Page 665: ...changed from port pins to SCI pins placing the pins into high impedance state 6 Set the value corresponding to the bit rate in BRR 7 Set the CKE 1 0 bits in SCR appropriately and set bits TIE RIE TE RE and TEIE in SCR to 0 at the same time When the CKE0 bit is set to 1 the SCKn pin is allowed to output clock pulses 8 Wait for at least a 1 bit interval and then set the TIE RIE TE and RE bits in SCR...

Page 666: ...s are automatically performed using a TXI interrupt request to activate the DTC or DMAC When the SSR TEND flag is set to 1 in transmission if the TIE bit in SCR is set to 1 a TXI interrupt request is generated The DTC or DMAC is activated by a TXI interrupt request if the TXI interrupt request is specified as a source of DTC or DMAC activation beforehand allowing transfer of transmit data The TEND...

Page 667: ...END flag generation timing Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5 etu 11 5 etu in block transfer mode SSR TEND flag TX interrrupt 11 0 etu DE Guard time When GM bit in SMR 0 Legend Ds Start bit D0 to D7 Data bits Dp Parity bit DE Error signal When GM bit in SMR 1 Note For the corresponding interrupt vector number see section 10 Interrupt Control Unit ICU Figure 20 26 SSR TEND Flag Generation ...

Page 668: ...eb 20 2013 Initialization No Write data to TDR Yes Clear bits TIE RIE and TE in SCR to 0 Start data transmission Start No No No Yes Yes Yes Yes No End TXI interrupt Error processing Error processing ERS 0 All data transmitted TXI interrupt ERS 0 Figure 20 27 Sample Serial Transmission Flowchart ...

Page 669: ...est to activate the DTC or DMAC In reception setting the RIE bit to 1 allows an RXI interrupt request to be generated The DTC or DMAC is activated by an RXI interrupt request if the RXI interrupt request is specified as a source of DTC or DMAC activation beforehand allowing transfer of receive data If an error occurs during reception and either the ORER or PER flag in SSR is set to 1 a receive err...

Page 670: ...Flowchart 20 5 8 Clock Output Control Clock output can be fixed using the CKE 1 0 bits in SCR when the GM bit in SMR is set to 1 Specifically the minimum width of a clock pulse can be specified Figure 20 30 shows an example of clock output stop timing when the CKE0 bit is controlled with GM 1 and CKE1 0 Given pulse width SCR CKE0 bit SCKn Given pulse width Figure 20 30 Clock Output Stop Timing At ...

Page 671: ...ection register DDR of Pm corresponding to the SCKn pin to the values for the output fixed state in software standby mode 2 Write 0 to the TE and RE bits in SCR to stop transmission reception Simultaneously set the CKE1 bit in SCR to the value for the output fixed state in software standby mode 3 Write 0 to the CKE0 bit in SCR to stop the clock 4 Wait for one cycle of the serial clock In the mean ...

Page 672: ...1 leads to generation of an ERI interrupt request If the TDR has not been updated by the time of transmission of the tail end bit of data being transmitted the SSR TEND flag is set to 1 and if the value of the SCR TEIE bit is 1 a TEI interrupt request is generated Writing of data to the TDR during TXI interrupt processing leads to clearing of the SSR TEND flag and clearing of the TEI interrupt at ...

Page 673: ...DMAC transfers the data If an error occurs the SCI automatically re transmits the same data During the retransmission the TEND flag is kept to 0 and the DTC or DMAC is not activated Therefore the SCI and DTC or DMAC automatically transmit the specified number of bytes including retransmission in the case of error occurrence However the ERS flag in SSR is not automatically cleared to 0 at error occ...

Page 674: ...ission To maintain the communications line in mark state the state of 1 until the TE bit is set to 1 to enable serial transmission set both Bj bit in DR of Pm and Bj bit in DDR of Pm to 1 Since the TE bit is cleared to 0 at this time the TxDn pin becomes an I O port and 1 is output from the TxDn pin To send a break during serial data transmission first set Bj bit in DDR of Pm 1 and Bj bit in DR of...

Page 675: ...ined To transmit data in the same transmission mode after cancellation of the power down state set the TE bit to 1 read SSR and write data to TDR sequentially to start data transmission To transmit data with a different transmission mode initialize the SCI first Figure 20 32 shows a sample flowchart for transition to software standby mode during transmission Figures 20 33 and 20 34 show the port p...

Page 676: ...r if the DTC has been activated the data remaining in the DTC will be transmitted when both the TE and TIE bits in SCR are set to 1 2 Clear the TIE and TEIE bits in SCR to 0 when they are 1 3 Setting for the module stop state is included Read TEND flag in SSR Figure 20 32 Example of Flowchart for Transition to Software Standby Mode during Transmission Port input output High output Port input outpu...

Page 677: ...t Last TxD bit retained Note Initialized in software standby mode Figure 20 34 Port Pin States during Transition to Software Standby Mode Internal Clock Clock Synchronous Transmission Start data reception Initialization SCR RE 1 SCR RE 0 Read receive data in RDR Make transition to software standby mode Cancel software standby mode No No Yes Yes RXI interrupt Change operating mode Data reception 1 ...

Page 678: ...EJ0120 Rev 1 20 Page 678 of 1006 Feb 20 2013 20 7 9 External Clock Input in Clock Synchronous Mode In clock synchronous mode the external clock SCKn must be input as follows High pulse period low pulse period 2 clock cycles or more period 6 clock cycles or more ...

Page 679: ... bits CRC processor unit Operation executed on eight bits in parallel CRC generating polynomial One of three generating polynomials selectable 8 bit CRC X 8 X 2 X 1 16 bit CRC X 16 X 15 X 2 1 X 16 X 12 X 5 1 CRC calculation switching CRC code generation for LSB first or MSB first communication selectable Power down function Module stop state can be set Note The circuit does not have functionality ...

Page 680: ...1 R W b2 LMS CRC Calculation Switching 0 Performs CRC operation for LSB first communication The lower order byte bits 7 to 0 is the first to be transmitted when the value of the CRCDOR CRC code are divided into bytes 1 Performs CRC operation for MSB first communication The higher order byte bits 15 to 8 is first to be transmitted when the value of the CRCDOR CRC code are divided into bytes R W b6 ...

Page 681: ...CRC operated are written 21 2 3 CRC Data Output Register CRCDOR b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0008 8282h CRCDOR is a 16 bit readable writable register that contains the result of CRC calculation In general the value will be 0 if there is no CRC error when the calculated CRC code matches the CRC code that continues on...

Page 682: ...0 1 1 0 0 0 0 0 0 0 0 CRCDIR CRC code generation 1 1 1 1 0 0 0 0 CRC code Output Data 7 7 7 F F F 0 8 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 2 Write F0h to CRCDIR 3 Read CRCDOR CRC code F78Fh 4 Serial transmission LSB first 1 Write 83h to CRCCR 0 0 0 0 0 0 0 0 CRCDOR 15 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 7 8 7 8 7 0 Figure 21 2 LSB First Data Transmission CRCDOR CRCCR Clear CRCDOR 1 7 ...

Page 683: ... 1 1 1 Input Data 7 F F F 0 8 7 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 7 0 7 0 7 0 7 0 7 0 7 7 0 7 0 CRC code CRC code generation 1 Serial reception LSB first 2 Write 83h to CRCCR 3 Write F0h to CRCDIR 4 Write 8Fh to CRCD 5 Write F7h to CRCDIR 6 Read CRCDOR CRC code 0000h no error CRCDIR CRCDIR 7 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC code generation CRC code generation 8 15 15 15 15 8 8...

Page 684: ...CDOR Clear CRCDOR 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDIR 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 7 0 7 0 7 0 7 0 7 0 7 7 0 7 0 CRC code generation 2 Write 87h to CRCCR 3 Write F0h to CRCDIR 4 Write EFh to CRCD 5 Write 1Fh to CRCDIR CRCDIR CRCDIR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC code generation CRC code generation 8 15 15 15 15 ...

Page 685: ...umption 21 5 Note on Transmission Note that the sequence of transmission for the CRC code differs according to whether transmission is LSB first or MSB first CRCDIR CRCDOR 1 CRC code CRC code generation After specifying the method for generation calculation write data to CRCDIR in order of 1 2 3 and 4 Output 15 7 7 0 0 0 0 7 0 0 0 0 7 7 7 7 1 CRC code H CRC code Output 7 7 0 0 0 0 0 0 7 7 7 7 2 Tr...

Page 686: ...matically suspended on detection of a not acknowledge bit For reception the acknowledge bit is automatically transmitted If a wait between the eighth and ninth clock cycles has been selected software control of the value in the acknowledge field in response to the received value is possible i e the return of ACK or NACK is selectable Wait function In reception the following periods of waiting can ...

Page 687: ...moval The interface incorporates digital noise filters for both the SCL and SDA signals and the width for noise cancellation by the filters is adjustable Interrupt sources Four sources Error in transfer or occurrence of events detection of AL NACK timeout a start condition including a restart condition or a stop condition Receive data full including matching with a slave address Transmit data empt...

Page 688: ... generator Transmission rece ption control circuit Transfer clock generator ACK output circuit SCLn SDAn NACK decision ACK reception circuit BC 2 0 CKS 2 0 CLO SDAI BBSY MST TRS SDA output delay control ST RS SP IICRST SDDL 2 0 PCLK ACKBR WAIT RDRFS NF 1 0 ACKBT NFE SARL0 SARL1 SARL2 SARU0 SARU1 SARU2 NACKF TXI TEI RXI STI SPI NAKI ALI TMOI Interrupt request NF 1 0 NFE FMPE FMPE MALE NALE SALE TMO...

Page 689: ...CLout SDAout SCLin SDAin SCLout SDAout SCLin SDAin SCLout SDAout Figure 22 2 Connections to the External Circuit by the I O Pins I2 C Bus Configuration Example Table 22 2 Pin Configuration Channel Pin Name I O Function RIIC0 SCL0 I O RIIC0 serial clock I O pin SDA0 I O RIIC0 serial data I O pin RIIC1 SCL1 I O RIIC1 serial clock I O pin SDA1 I O RIIC1 serial data I O pin ...

Page 690: ...rate low level register ICBRL FFh 0008 8310h 8 I2 C bus bit rate high level register ICBRH FFh 0008 8311h 8 I2 C bus transmit data register ICDRT FFh 0008 8312h 8 I2 C bus receive data register ICDRR 00h 0008 8313h 8 I2 C bus shift register ICDRS 8 RIIC1 I2 C bus control register 1 ICCR1 1Fh 0008 8320h 8 I2 C bus control register 2 ICCR2 00h 0008 8321h 8 I2 C bus mode register 1 ICMR1 08h 0008 832...

Page 691: ...RX610 Group 22 I 2 C Bus Interface RIIC R01UH0032EJ0120 Rev 1 20 Page 691 of 1006 Feb 20 2013 Channel Register Name Symbol Value after Reset Address Access Size RIIC1 I2 C bus shift register ICDRS 8 ...

Page 692: ...state Write 0 Changes the SCLn pin output to a low level 1 Changes the SCLn pin in a high impedance state High level output is achieved through an external pull up resistor R W 1 2 b4 SOWP SCLO SDAO Write Protect 2 0 Allows the SCLO and SDAO bits to be rewritten This bit is always read as 1 R W 2 b5 CLO Extra SCL Clock Cycle Output 0 Does not output an extra SCL clock cycle default 1 Outputs an ex...

Page 693: ...his function see section 22 11 2 Extra SCL Clock Cycle Output Function IICRST Bit I 2 C Bus Interface Internal Reset This bit is used to reset the internal states of the RIIC Setting this bit to 1 initiates an RIIC reset or internal reset Whether an RIIC reset or internal reset is initiated is determined according to the combination with the ICE bit Table 22 4 lists the resets of the RIIC The RIIC...

Page 694: ...asynchronously Table 22 4 RIIC Resets IICRST ICE State Specifications 1 0 RIIC reset Resets all registers and internal states of the RIIC 1 Internal reset Reset the BC 2 0 bits in ICMR1 and the ICSR1 ICSR2 ICDRS registers and the internal states of the RIIC ICE Bit I 2 C Bus Interface Enable This bit is used to enable or disable the transfer operation of the RIIC When this bit is set to 0 to disab...

Page 695: ... I2 C bus is occupied bus busy state or in the bus free state R Note When the MTWP bit in ICMR1 is set to 1 the MST and TRS bits can be written to ICCR2 has a flag function that indicates whether or not the I2 C bus is occupied and whether the RIIC is in transmit receive or master slave mode as well as a function to issue a start or stop condition ST Bit Start Condition Issuance Request This bit i...

Page 696: ...in this mode but the restart condition issuance request bit remains set If the operating mode changes to master mode with the bit not being cleared the restart condition may be issued this may hinder communications or cause an unexpected action SP Bit Stop Condition Issuance Request This bit is used to request that a stop condition be issued in master mode When this bit is set to 1 to request to i...

Page 697: ...slave mode a match between the received address and the address enabled in ICSER when the value of the received R W bit is 0 including cases where the received address is the general call address In slave mode a restart condition is detected a start condition is detected with ICCR2 BBSY 1 and ICCR2 MST 0 When 0 is written to the TRS bit with the MTWP bit in ICMR1 set to 1 When 1 is written to the ...

Page 698: ...start condition has been issued When the SDAn line changes from low to high under the condition of SCLn high this bit is cleared to 0 after the bus free time specified in ICBRL start condition is not detected assuming that a stop condition has been issued Setting condition When a start condition is detected Clearing conditions When the bus free time specified in ICBRL start condition is not detect...

Page 699: ... to the MST and TRS bits in ICCR2 1 Enables writing to the MST and TRS bits in ICCR2 R W Note Set the BCWP bit to 0 to rewrite the BC 2 0 bits The BC 2 0 bits must be rewritten by using the MOV instruction ICMR1 specifies the internal reference clock source within the RIIC indicates the number of bits to be transferred and protects the MST and TRS bits in ICCR2 from being written BC 2 0 Bits Bit C...

Page 700: ... BCWP Bit BC Write Protect This bit enables a value to be written in the BC 2 0 bits CKS 2 0 Bits Internal Reference Clock Selection These bits select a reference clock source IICφ inside the RIIC MTWP Bit MST TRS Write Protect This bit controls the modification of the MST and TRS bits in ICCR2 ...

Page 701: ...r timeout is disabled 1 Writing to the internal counter for timeout is enabled When this bit is set to 1 the address of timeout internal counter TMOCNTL U is allocated to the address of SARL0 SARU0 R W b6 to b4 SDDL 2 0 SDA Output Delay Counter When ICMR2 DLCS 0 IICφ b6 b4 0 0 0 No output delay 0 0 1 1 IICφ cycle 0 1 0 2 IICφ cycles 0 1 1 3 IICφ cycles 1 0 0 4 IICφ cycles 1 0 1 5 IICφ cycles 1 1 0...

Page 702: ... timeout detection function is enabled TMOE bit 1 in ICFER TMWE Bit Enable Writing to the Internal Counter for Timeout This bit is used to select whether the slave address register SARL0 SARU0 is assigned to the internal counter for timeout TMOCNTL TMOCNTU SDDL 2 0 Bits SDA Output Delay Setup Counter The SDA output can be delayed by the SDDL 2 0 setting This counter works with the clock source sel...

Page 703: ...odification of the ACKBT bit is disabled 1 Modification of the ACKBT bit is enabled 1 W 1 b5 RDRFS RDRF Flag Set Timing Selection 2 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle The SCLn line is not held low at the falling edge of the eighth clock cycle 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle The SCLn line is held low at the falling edge of ...

Page 704: ...tion When 1 is written to this bit with the ACKWP bit set to 1 Clearing conditions When 0 is written to this bit with the ACKWP bit set to 1 When stop condition issuance is detected when a stop condition is detected with the SP bit in ICCR2 set to 1 When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 RIIC reset Note The ACKBT bit must be modified while the ACKWP bit is 1 I...

Page 705: ...tinued without holding the period between the ninth and the first SCL clock cycle low When both the RDRFS and WAIT bits are 0 continuous receive operation is enabled with the double buffer When the WAIT bit is 1 the SCLn line is held low from the falling edge of the ninth clock cycle until the ICDRR value is read each time single byte data is received This enables receive operation in byte units N...

Page 706: ...on is disabled 1 Slave arbitration lost detection is enabled R W b4 NACKE NACK Reception Transfer Suspension Enable 0 Transfer operation is not suspended during NACK reception transfer suspension disabled 1 Transfer operation is suspended during NACK reception transfer suspension enabled R W b5 NFE Digital Noise Filter Circuit Enable 0 No digital noise filter circuit is used 1 A digital noise filt...

Page 707: ...CL Synchronous Circuit Enable This bit is used to specify whether to synchronize the SCL clock with the SCL input clock Normally set this bit to 1 When the SCLE bit is cleared to 0 SCL synchronous circuit is invalid the RIIC does not synchronize the SCL clock with the SCL input clock by detecting the SCLn line level for the SCL clock output operation in master mode and the RIIC outputs the SCL clo...

Page 708: ...d 1 General call address detection is enabled R W b4 Reserved This bit is always read as 0 The write value should always be 0 R W b5 DIDE Device ID Address Detection Enable 0 Device ID address detection is disabled 1 Device ID address detection is enabled R W b6 Reserved This bit is always read as 0 The write value should always be 0 R W b7 HOAE Host Address Enable 0 Host address detection is disa...

Page 709: ... to 1 if the received first frame matches the device ID the RIIC recognizes that the Device ID address has been received When the following R W bit is 0 W the RIIC recognizes the second and the following frames as slave addresses and continues the receive operation When this bit is cleared to 0 the RIIC ignores the received first frame even if it matches the device ID address and recognizes the fi...

Page 710: ...pt request NAKI is enabled R W b5 RIE Receive Data Full Interrupt Enable 0 Receive data full interrupt request ICRXI is disabled 1 Receive data full interrupt request ICRXI is enabled R W b6 TEIE Transmit End Interrupt Enable 0 Transmit end interrupt request ICTEI is disabled 1 Transmit end interrupt request ICTEI is enabled R W b7 TIE Transmit Data Empty Interrupt Enable 0 Transmit data empty int...

Page 711: ... the NACKF flag in ICSR2 is set to 1 An NAKI interrupt request is canceled by clearing the NACKF flag or the NAKIE bit to 0 RIE Bit Receive Data Full Interrupt Enable This bit is used to enable or disable receive data full interrupt requests ICRXI when the RDRF flag in ICSR2 is set to 1 TEIE Bit Transmit End Interrupt Enable This bit is used to enable or disable transmit end interrupts ICTEI when ...

Page 712: ...1 value in SARL1 while the FS bit in SARU1 is 0 7 bit address format selected This bit is set to 1 when the received slave address matches a value of 1111 0b SVA 9 8 in SARU1 and the following address matches the SARL1 value while the FS bit in SARU1 is 1 10 bit address format selected This bit is set at the rising edge of the ninth SCL clock cycle in the SARL1 match determination frame R W b2 AAS...

Page 713: ... the received slave address matches a value of 1111 0b SVA 9 8 in SARUy and the following address matches the SARLy value with the SARyE bit in ICSER set to 1 slave address m detection enabled This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame Clearing conditions When 0 is written to the AASy bit after reading AASy 1 When a stop condition is detected When 1 is writt...

Page 714: ...tely after a start condition or restart condition is detected matches a value of device ID 1111 100b 0 W with the DIDE bit in ICSER set to 1 Device ID address detection enabled This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame Clearing conditions When 0 is written to the DID bit after reading DID 1 When a stop condition is detected When the first frame received imm...

Page 715: ... ninth SCL clock cycle in the frame Clearing conditions When 0 is written to the HOA bit after reading HOA 1 When a stop condition is detected When 0 is written to the SMBS bit in ICMR3 or the HOAE bit in ICSER When the received slave address does not match the host address 0001 000b with the HOAE bit in ICSER set to 1 host address detection enabled This flag is cleared to 0 at the rising edge of ...

Page 716: ...is detected R W b5 RDRF Receive Data Full Flag 0 ICDRR contains no receive data 1 ICDRR contains receive data R W b6 TEND Transmit End Flag 0 Data is being transmitted 1 Data has been transmitted R W b7 TDRE Transmit Data Empty Flag 0 ICDRT contains transmit data 1 ICDRT contains no transmit data R Note Only 0 can be written to clear the flag ICSR2 indicates various interrupt request flags and sta...

Page 717: ...n the ST bit in ICCR2 is set to 1 start condition issuance request with the BBSY flag in ICCR2 set to 1 When NACK arbitration lost detection is enabled ICFER MALE 1 When the internal SDA output state does not match the SDAn line level at the rising edge of SCL clock in the ACK period during NACK transmission in receive mode When slave arbitration lost detection is enabled When the internal SDA out...

Page 718: ...fer suspension enabled Clearing conditions When 0 is written to the NACKF bit after reading NACKF 1 When 1 is written to the IICRST bit in ICCR1 to apply an RIIC reset or an internal reset Note When the NACKF flag is set to 1 the RIIC suspends data transmission reception Writing to ICDRT in transmit mode or reading from ICDRR in receive mode with the NACKF flag set to 1 does not enable data transm...

Page 719: ... a restart condition is detected b When the RIIC enters transmit mode from receive mode c When 1 is written to while the ICMR1 MTWP bit is 1 When the received slave address matches while the TRS bit is 1 Clearing conditions When data is written to ICDRT When the TRS bit in ICCR2 is cleared to 0 a When a stop condition is detected b When the RIIC enters receive mode from transmit mode c When 0 is w...

Page 720: ... format these bits form a 7 bit slave address When the FS bit in SARUy is 1 10 bit address format these bits form the lower 8 bit address combined with the SVA0 bit of a 10 bit slave address R W SARLy sets slave address y 7 bit address or lower eight bits of 10 bit address SVA0 Bit 10 Bit Address LSB When the 10 bit address format is selected SARUy FS 1 this bit functions as the LSB of a 10 bit ad...

Page 721: ...ress format and sets the upper bits of a 10 bit slave address FS Bit 7 Bit 10 Bit Address Format Selection This bit is used to select 7 bit address or 10 bit address for slave address m in SARLy and SARUy When the SARyE bit in ICSER is set to 1 SARLy and SARUy enabled and the SARUy FS bit is 0 the 7 bit address format is selected for slave address m the SVA 7 1 setting in SARLy is valid and the se...

Page 722: ...s 1 The write value should always be 1 R W ICBRL is a 5 bit register to set the low level period of SCL clock It also works to generate the data setup time for automatic SCL low hold operation see section 22 8 Function to Automatically Hold SCLn Clock Low when the RIIC is used only in slave mode this register needs to be set to a value longer than the data setup time ICBRL counts the low level per...

Page 723: ... is valid in master mode If the RIIC is used only in slave mode this register need not to set the high level period ICBRH counts the high level period with the internal reference clock source IICφ specified by the CKS 2 0 bits in ICMR1 The I2 C transfer rate and the SCL clock duty ratio are calculated using the following expression Transfer rate 1 ICBRH 1 ICBRL 1 IICφ 1 SCLn line rising time tr SC...

Page 724: ...1 F5h 24 F8h 100b 12 ECh 15 EFh 100 010b 15 EFh 18 F2h 010b 19 F3h 23 F7h 010b 24 F8h 29 FDh 400 000b 9 E9h 20 F4h 000b 11 EBh 25 F9h 001b 7 E7h 16 F0h 1000 000b 4 E4h 7 E7h 000b 5 E5h 9 E9h 000b 6 E6h 12 ECh Transfer Rate kbps Operating Frequency PCLK MHz 30 33 50 CKS 2 0 ICBRH ICBRL CKS 2 0 ICBRH ICBRL CKS 2 0 ICBRH ICBRL 10 110b 20 F4h 24 F8h 110b 22 F6h 26 FAh 111b 16 F0h 20 F4h 50 100b 15 EFh...

Page 725: ...5 b4 b3 b2 b1 b0 Value after reset 0 0 0 0 0 0 0 0 ICDRR is an 8 bit read only register that stores receive data When one byte of data has been received the received data is transferred from the I2 C bus shift register ICDRS to ICDRR to enable the next data to be received The double buffer structure of ICDRS and ICDRR allows continuous receive operation if the received data has been read from ICDR...

Page 726: ...ecause these are the same registers as SARL0 and SARU0 Bit Symbol Bit Name Description R W b15 to b8 TMOCNTU Internal Counter for Timeout Higher order bits of the internal counter for timeout 1 W 2 b7 to b0 TMOCNTL Lower order bits of the internal counter for timeout W 2 Notes 1 Bits 15 to 12 become reserved bits when TMOS 1 short mode Although they are still writable values written have no effect...

Page 727: ... n n 1 or more n n 1 or more n Number of transfer frames Figure 22 3 I2 C Bus Format S SLA R W A Data A Data A P SDA 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SCL Figure 22 4 I2 C Bus Timing SLA 7 Bits Legend S Start condition The master device drives the SDAn line low from high level while the SCLn line is at a high level SLA Slave address by which the master device selects a slave device R W Indicates th...

Page 728: ...ed Set SARLn and SARUn Set ICSER Set slave address format and slave address RIIC transfer operation enabled Set interrupt enable Legend n 0 to 2 Set ICIER Set ICE in ICCR1 to 1 End Notes 1 When the RIIC is used only in slave mode set the ICBRL register to a value longer than the data setup time 2 Set these registers as necessary 3 This is the case when the timeout function is in use this processin...

Page 729: ...ally set to 1 in response to setting of the TRS bit to 1 3 Check that the TDRE flag in ICSR2 is 1 and then write the value for transmission the slave address and the R W bit to ICDRT Once the data for transmission are written to ICDRT the TDRE flag is automatically cleared to 0 the data are transferred from ICDRT to ICDRS and the TDRE flag is again set to 1 After the byte containing the slave addr...

Page 730: ...nitial settings 2 Check I2 C bus occupation and issue a start condition 6 Check stop condition issuance 7 Processing for the next transfer operation Yes 5 Check end of last data transmission and issue a stop condition 3 Transmit slave address and W first byte 4 Check ACK and set transmit data ICSR2 NACKF 0 TMOCNT 0000h TMOCNT 0000h TMOCNT 0000h 1 1 1 Note1 Internal counter for timeout This is the ...

Page 731: ...ic low hold to prevent wrong transmission Figure 22 7 Master Transmit Operation Timing 1 7 Bit Address Format ransmit data upper 10 bits W 0 ACK Write ICDRT 11110b 2 bits W Write ICDRT lower 8 bits Write ICDRT DATA 1 Write ICDRT DATA2 Write 1 to ST RDR F ICDR R TDR E MS T TR S BBS Y TEN D S 9 SCL n SDA n S T STAR T ICDR T ICDR S Upper 10 bits W Lower 10 bits Lower 10 bits DATA 1 DATA 2 DATA 1 Uppe...

Page 732: ... 8 b0 8 b0 1 b7 7 b1 9 DATA n 1 DATA n 1 DATA n DATA n 2 9 9 XXXX Initial value final receive data 5 Write SP 1 4 Clear STOP 0 7 P Write ICDRT Final transmit data DATA n 0 ACK 0 ACK 0 ACK DATA n 2 TDRE MST TRS BBSY TEND SCLn SDAn STOP ICDRT ICDRS SP RDRF ICDRR ACKBT ACKBR A NA ACK X ACK NACK Transmit data DATA n 1 Transmit data DATA n ACK Figure 22 9 Master Transmit Operation Timing 3 ...

Page 733: ...for the SDA output and the levels on the SDAn line have matched while the ST bit is 1 the RIIC recognizes that issuing of the start condition as requested by the ST bit has been successfully completed and the MST and TRS bits in ICCR2 are automatically set to 1 placing the RIIC in master transmitter mode The TDRE flag in ICSR2 is also automatically set to 1 in response to setting of the TRS bit to...

Page 734: ...to the low level on the rising edge of the ninth clock cycle in reception of the last byte so the state is such that issuing a stop condition is possible 6 When the ICMR3 RDRFS bit is 0 and the slave device must be notified that it is to end transfer for data reception after transfer of the next final byte set the ACKBT bit in ICMR3 to 1 NACK 7 After reading out the byte before last from the ICDRR...

Page 735: ...ad received data and prepare for receiving final data 6 Change the timing of setting of the RDRF set the NACK and read data of final byte 1 7 Read final data and issue a stop condition 8 Check stop condition issuance 9 Processing for the next transfer operation No ICSR2 TDRE 1 ICSR2 RDRF 1 ICSR2 RDRF 1 ICCR2 BBSY 0 Next data final byte 2 ICMR3 WAIT 1 No Yes TMOCNT 0000h TMOCNT 0000h TMOCNT 0000h I...

Page 736: ...1 7 Bit Address Format when RDRFS 0 Write 1 to ST Write data to ICDRT 11110b 2 bits R 0 ACK XXXX Initial value last data for reception Upper 10 bits R Upper 10 bits R Upper 10 bits R Master transmit mode Master receive mode Automatic low hold error transmission protected Read ICDRR Dummy read 11110b 2 bits R Upper 10 bits W TDRE MST TRS BBSY TEND S SCLn SDAn ST START ICDRT ICDRS DATA 1 W 7 b1 1 b7...

Page 737: ...4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 8 b0 1 b7 7 b1 DATA n 2 SP DATA n DATA n 2 RDRF ICDRR DATA n 3 WAIT 9 NACK ACKBT ACKBR 6 7 5 9 P 9 DATA n 1 DATA n 1 DATA n 2 0 ACK 0 ACK 0 ACK 1 NACK Clear WAIT to 0 Write 1 to SP Write 1 to WAIT Write 1 to ACKBT Read ICDRR DATA n 1 Read ICDRR DATA n 2 0 ACK ACK Receive data DATA n 1 Receive data DATA n XXXX last data for transmission 7 bit addresses R Upper 10 bits ...

Page 738: ...edge bit on the ninth cycle of SCL clock If the value of the R W bit that was also received at this time is 1 the RIIC automatically places itself in slave transmitter mode by setting both the TRS bit and the TDRE flag in ICSR2 to 1 3 After the ICSR2 TEND flag is confirmed to be 1 write the data for transmission to the ICDRT register At this time if the RIIC receives no acknowledge from the master...

Page 739: ...settings 2 3 Check ACK and set transmit data Checking of ACK not necessary immediately after address is received 5 Check stop condition detection Yes 4 Dummy read to release the SCL 6 Processing for the next transfer operation Initial settings ICSR2 TEND 1 ICSR2 STOP 1 Note1 This is the case when the timeout function is in use this processing is not required if the function is not in use 1 TMOCNT ...

Page 740: ...s R XXXX Initial value last data for reception 0 ACK X ACK NACK 0 ACK Write data to ICDRT DATA2 Write data to ICDRT DATA3 ACK ACK Transmit data DATA 2 Figure 22 15 Slave Transmit Operation Timing 1 7 Bit Address Format TDRE MST TRS BBSY TEND SCLn SDAn STOP ICDRT ICDRS DATA n DATA n 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 1 b7 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 8 b0 1 b7 7 b1 DATA n 1 DATA n 1 DATA n DA...

Page 741: ...bit to the acknowledge bit on the ninth cycle of SCL clock If the value of the R W bit that was also received at this time is 1 the RIIC continues to place itself in slave receiver mode and sets the RDRF flag in ICSR2 to 1 3 After the ICSR2 STOP flag is confirmed to be 0 and the ICSR2 RDRF flag to be 1 dummy read ICDRR the dummy value consists of the slave address and R W bit when the 7 bit addres...

Page 742: ...l data received No End of slave reception ICSR2 STOP 0 Yes ICSR2 RDRF 1 ICSR2 STOP 1 No Yes Read ICDRR last data 1 Initial settings 6 Processing for the next transfer 5 Check stop condition detection Yes No Note1 This is the case when the timeout function is in use this processing is not required if the function is not in use 1 TMOCNT 0000h TMOCNT 0000h 1 1 TMOCNT 0000h Figure 22 17 Example of Sla...

Page 743: ...ata DATA 1 XXXX Initial value last data for transmission 7 bit address W 0 ACK 0 ACK Read ICDRR DATA 1 ACK ACK Figure 22 18 Slave Receive Operation Timing 1 7 Bit Address Format when RDRFS 0 XXXX Initial value last data for transmission 0 ACK Read ICDRR DATA n 2 TDRE MST TRS BBSY TEND SCLn SDAn STOP ICDRT ICDRS DATA n 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 1 b7 2 b6 4 b4 5 b3 6 b2 7 b1 3 b5 8 b0 8 b0 ...

Page 744: ...t low level specified in ICBRL When the RIIC finishes counting out the width at low level it stops driving the SCLn line to the low level i e releases the line At this time if the width at low level of the SCL clock signal from the other master device is longer than the width at low level set in the RIIC the width at low level of the SCL signal will be extended Once the width at low level for the ...

Page 745: ...n 000b the DLCS bit in IMCR2 selects the clock source for counting by the SDA output delay counter as the internal base clock IICφ for the IIC module or as a clock signal derived by dividing the frequency of the internal base clock by two IICφ 2 The counter counts the number of cycles set in the SDDL 2 0 bits in IMCR2 After counting of the set number of cycles of delay is completed the RIIC module...

Page 746: ...n the input signal level matches the output level of the number of effective flip flop circuit stages as selected by the NF 1 0 bits in ICMR3 the signal level is conveyed to the subsequent stage If the signal levels do not match the previous value is retained If the ratio between the frequency of the internal operating clock PCLK and the transfer rate is small e g data transfer at 400 kbps with PC...

Page 747: ... ICSR2 is set to 1 by the following R W bit This causes a receive data full interrupt ICRXI or transmit data empty interrupt ICTXI to be generated The AASy flag is used to identify which slave address has been specified Figures 22 23 to 22 25 show the AASy flag set timing in three cases TDRE AASn S 1 2 3 4 5 6 7 7 bit slave address 8 W 1 8 R 9 ACK TRS 9 ACK BBSY TDRE AASn TRS BBSY RDRF RDRF 2 3 4 ...

Page 748: ...ted Upper 2 bits Address match AAS 1 AAS 2 AAS 0 BBS Y 1 W 1 1 1 0 Lower 8 bits R W Address match AAS 1 AAS 2 AAS 0 BBS Y Address mismatch Address match SCL n SDA n SCL n SDA n W DAT A 1 1 1 1 0 R W AAS 1 AAS 2 AAS 0 BBS Y S 7 bit slave address SAR0L Address mismatch Address match SCL n SDA n DAT A R W 7 bit slave address SAR1L R W Address match Address mismatch S 9 Sr 2 3 4 5 6 7 1 1 to 8 9 8 3 4...

Page 749: ...SR1 and the RDRF flag in ICSR2 are set to 1 on the falling edge of the ninth cycle of SCL clock This leads to the generation of a receive data full interrupt ICRXI The value of the GCA flag can be confirmed to recognize that the general call address has been transmitted Operation after detection of the general call address is the same as normal slave receive operation AAS2 AAS0 S 2 3 4 5 6 7 0 0 0...

Page 750: ...uent bytes and sets the ICSR2 TDRE flag to 1 In the device ID address detection function the RIIC clears the DID flag to 0 if a match with the RIIC s own slave address is not obtained or a match with the device ID address is not obtained after a match with the RIIC s own slave address and the detection of a restart condition If the first byte after detection of a start or restart condition matches...

Page 751: ...DID R W Address mismatch Device ID mismatch RDRF SCLn SDAn SCLn SDAn W W 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 7 bit slave address other station AASn BBSY DID TDRE SCLn SDAn 0 0 1 1 1 1 R NACK NACK 1 0 0 1 1 1 1 R NACK Comparing the second and the following bytes is stopped RDRF ACK ACK ACK 1 1 1 Read ICDRR Dummy read 7 bit address lower 10 bits S 9 Sr 2 3 4 5 6 7 1 1 to 8 9 8 3 4 5 6 7 9 8 1 2 Rece...

Page 752: ...n the R W bit is 0 Wr bit This causes a transmit data empty interrupt ICTXI to be generated The HOA flag is used to recognize that the host address was sent from the smart battery or other devices If the bit following the host address 0001 000b is an Rd bit R W bit 1 the RIIC can also detect the host address After the host address is detected the RIIC operates in the same manner as normal slave op...

Page 753: ...ock cycle of the next Slave transmitter mode Low level interval between the ninth clock cycle of one transfer and the first clock cycle of the next 8 R 9 ACK TDRE AASn TRS BBSY RDRF S 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 ACK 2 3 Master transmit mode Slave transmit mode TDRE AASn TRS BBSY RDRF S 2 3 4 5 6 7 2 3 4 5 6 7 8 9 ACK 8 W 9 ACK 2 SCLn SDAn SCLn SDAn 1 1 1 1 1 Data DATA1 7 bit slave address Data D...

Page 754: ...to 0 In master transmit mode clear the NACKF flag to 0 issue a restart or stop condition and then issue a start condition again ACK NACK ACK Transfer suspended Transmit data DATA2 Write data to ICDRT 7 bit address W TDRE AASn TRS BBSY NACKF S 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 Master transmit mode Slave transmit mode TDRE AASn TRS BBSY NACKF S 2 3 4 5 6 7 8 W 9 S 2 3 4 5 6 7 8 W 9 8 W 9 P P SCLn SDAn S...

Page 755: ...s the ACKBT bit value in ICMR3 for the acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL clock cycle and automatically holds the SCLn line low at the falling edge of the ninth SCL clock cycle using the WAIT bit function This low hold is released by reading data from ICDRR which enables bytewise receive operation The WAIT bit func...

Page 756: ...ic low hold RDRFS RDRFS 1 WAIT 0 RDRFS 1 WAIT 1 Write 0 to ACKBT Read ICDRR Read ICDRR Write 0 to ACKBT ACK Data ACK Data ACK Automatic low hold RDRFS Automatic low hold WAIT Automatic low hold RDRFS Write 0 to ACKBT Read ICDRR Read ICDRR Write 0 to ACKBT 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 1 9 9 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 9 9 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 9 1 9 2 ...

Page 757: ...on while transfer is in progress When a start condition is issued successfully if the data for transmission including the address bits i e the internal SDA output level and the level on the SDAn line do not match the high output as the internal SDA output i e the SDAn pin is in the high impedance state and the low level is detected on the SDAn line the RIIC loses in arbitration After a loss in arb...

Page 758: ...MST BBSY GCA RDRF SCLn SDAn SCLn SDAn TRS AL MST BBSY AASn TDRE SCLn SDAn SCLn SDAn Transmit data mismatch Arbitration lost Release SCLn SDA ACK ACK ACK Clear AL to 0 Clear AL to 0 ACK ACK Receive data Figure 22 32 Examples of Master Arbitration Lost Detection MALE 1 S PCLK S 1 S 8 R 9 1 2 1 2 6 7 1 ACK 7 bit 10 bit slave address ST 1 BBSY 1 Bus free BBSY 0 start condition issuance ST 1 error Bus ...

Page 759: ...e connected through the bus In this example master A receives two bytes of data from the slave device and master B receives four bytes of data from the slave device If master A and master B access the slave device simultaneously because the slave address is identical arbitration is not lost in both master A and master B during access to the slave device Therefore both master A and master B recogni...

Page 760: ...tection function is mainly used when transmitting a UDID Unique Device Identifier over an SMBus When it loses slave arbitration the RIIC is immediately released from the slave matched state and enters slave receiver mode This function can detect conflicts of data during transmission of UDIDs over an SMBus and eliminates subsequent redundant processing processing for the transmission of FFh The RII...

Page 761: ... Detect low level of the SCLn line and ensure the low level period of SCLn set in ICBRL 22 10 2 Issuing a Restart Condition The RIIC issues a restart condition when the RS bit in ICCR2 is set to 1 When the RS bit is set to 1 a restart condition issuance request is made and the RIIC issues a restart condition when the BBSY flag in ICCR2 is 1 bus busy and the MST bit in ICCR2 is 1 master mode A rest...

Page 762: ...ondition issuance request is made and the RIIC issues a stop condition when the BBSY flag in ICCR2 is 1 bus busy and the MST bit in ICCR2 is 1 master mode A stop condition is issued in the following sequence Stop condition issuance Drive the SDAn line low high level to low level Ensure the low level period of SCLn line set in ICBRL Release the SCLn line low level to high level Detect a high level ...

Page 763: ...redetermined time The timeout detection function monitors the SCLn line state and counts the low level period or high level period using the internal counter The timeout detection function resets the internal counter each time the SCLn line changes rising or falling but continues to count unless the SCLn line changes If the internal counter overflows due to no SCLn line change the RIIC can detect ...

Page 764: ...r counter Clear counter Clear counter Start counter Start counter Start counter 16 bit counter overflows 14 bit counter overflows Write 1 to TMOL Write 0 to TMOE Write 0 to TMOL Write 1 to TMOH Clear counter Start counter Example of operation when TMOH 1 and TMOL 1 BBSY SCLn SDAn TMOF TMOE Clear counter Clear counter ST When a stat condition is issued In the slave address matched state Timeout det...

Page 765: ...le is in master mode and the slave device is holding the SDAn line at the low level because synchronization with the slave device has been lost due to the effects of noise etc the output of a stop condition is not possible The facility for output of an extra cycle of the SCL clock signal can be used to output extra cycles of SCL one by one to make the slave device release the SDAn line from being ...

Page 766: ...while retaining other settings After issuing a reset be sure to clear the IICRST bit in ICCR1 to 0 Both types of reset are effective for release from bus hung states since both restore the output state of the SCLn and SDAn pins to the high impedance state Issuing a reset during slave operation may lead to a loss of synchronization between the master device clock and the slave device clock so avoid...

Page 767: ... of the RIIC The measured timeout period must be within the total clock low level period slave device TLOW SEXT 25 ms max of the SMBus standard If the time measured with the TPU or TMR exceeds the clock low level detection timeout TTIMEOUT 25 ms min of the SMBus standard the slave device must release the bus by writing 1 to the IICRST bit in ICCR1 to issue an internal reset of the RIIC When an int...

Page 768: ... A NA Figure 22 40 SMBus Timeout Measurement 22 12 2 Packet Error Code PEC The RX610 Group incorporates a CRC operation circuit The CRC operation circuit enables transmission of a packet error code PEC or checking the received data of the SMBus in data communication of the RIIC For the CRC generating polynomials of the CRC operation circuit see section 21 CRC Operation Circuit CRC The PEC data in ...

Page 769: ... host for its own slave address or to request its own slave address from the SMBus host For a product of the RX610 Group to operate as an SMBus host or ARP master the host address 0001 000b sent from the slave device must be detected as a slave address so the RIIC has a function for detecting the host address To detect the host address as a slave address set the SMBS bit in ICMR3 and the HOAE bit ...

Page 770: ...upt sources during interrupt handling Notes on interrupt processing 1 There is a latency delay between the execution of a write instruction for a peripheral module by the CPU and actual writing to the module Thus when an interrupt flag has been cleared or masked read the relevant flag again to check whether clearing or masking has been completed and then return from interrupt processing Returning ...

Page 771: ...a reset Retained Operation retained Operation retained ICFER At a reset At a reset Retained Operation retained Operation retained ICSER At a reset At a reset Retained Operation retained Operation retained ICIER At a reset At a reset Retained Operation retained Operation retained ICSR1 At a reset At a reset At a reset Operation retained At a reset ICSR2 TDRE TEND At a reset At a reset At a reset Op...

Page 772: ...less of the setting in the RDRF flag set timing selection ICMR3 RDRFS bit The ACKBT value written after the falling edge of the eighth SCL clock cycle is output at the falling edge of the eighth clock cycle of the next frame 22 15 4 Restrictions on Timings for Stop Condition Issuance Request and Transmit Data Writing in Master Transmitter Mode In master transmitter mode when the low level output i...

Page 773: ...ta in ICDRT that has not been transmitted might be output To restart the communication after the NACK is received make sure to end the communication once by issuing the stop condition and then restart the communication by issuing the start condition 22 15 6 Notes on the RDRF Flag Set Timing Selection Bit RDRFS In slave mode slave addresses are matched while the RDRF flag set timing selection bit R...

Page 774: ... operating peripheral module clock PCLK 50 MHz A D conversion clock 4 types PCLK PCLK 2 PCLK 4 PCLK 8 Operating modes Single mode A D conversion is to be performed for only once on the analog input of the specified single channel Scan mode Continuous scan mode A D conversion is to be performed sequentially on the analog inputs of the specified channels up to four Single scan mode A D conversion is...

Page 775: ...er Compare match input capture from TPU0 TGRA TGRB TGRC TGRD Compare match input capture from TPU0 to TPU5 TGRA TGRA TGRA TGRA Compare match input capture from TPU6 to TPU11 TGRA TGRA TGRA TGRA Compare match from TMR0 Compare match A Compare match A Compare match from TMR2 Compare match A Compare match A Interrupt ADI0 ADI1 ADI2 ADI3 Module stop function setting 2 MSTPCRA MSTPA23 bit MSTPCRA MSTPA...

Page 776: ...terrupt signal AD0 ADDRD A D data register D VREFH VREFL ADTRG0 AD0 ADDRA A D data register A AD0 ADDRB A D data register B AD0 ADDRC A D data register C AD0 ADDPR AD0 ADSSTR Compare match input capture A signals from TPU0 to TPU5 TPU6 to TPU11 Compare match input capture A signal from TPU0 AD0 ADCR A D control register AD0 ADDPR ADDRy format select Clock selec ion PCLK PCLK 2 PCLK 4 ADCLK Interna...

Page 777: ...it ADI1 interrupt signal AD1 ADDRD A D data register D VREFH VREFL ADTRG0 AD1 ADDRA A D data register A AD1 ADDRB A D data register B AD1 ADDRC A D data register C AD1 ADDPR AD1 ADSSTR AD1 ADCSR A D control status register AD1 ADCR A D control register AD1 ADDPR ADDRy format select ADCLK ADTRG1 Clock selection PCLK PCLK 2 PCLK 4 Internal clock PCLK 8 Bus interface Compare match A signal from TMR0 ...

Page 778: ...ple and hold circuit ADI2 interrupt signal AD2 ADDRD A D data register D VREFH VREFL ADTRG2 AD2 ADDRA A D data register A AD2 ADDRB A D data register B AD2 ADDRC A D data register C AD2 ADDPR AD2 ADSSTR AD2 ADCSR A D control status register AD2 ADCR A D control register AD2 ADDPR ADDRy format select Clock selection PCLK PCLK 2 PCLK 4 ADCLK Internal clock PCLK 8 Compare match A signal from TMR2 Com...

Page 779: ...e and hold circuit Compare match A signal from TMR2 ADI3 interrupt signal AD3 ADDRD A D data register D VREFH VREFL ADTRG2 AD3 ADDRA A D data register A AD3 ADDRB A D data register B AD3 ADDRC A D data register C AD3 ADDPR AD3 ADSSTR Compare match input capture A signals from TPU0 to TPU5 TPU6 to TPU11 Compare match input capture D signal from TPU0 AD3 ADCSR A D control status register AD3 ADCR A ...

Page 780: ...ting A D conversion ADTRG1 Input External trigger input pin for starting A D conversion 2 AD2 AN8 to AN11 Input Analog input pins ADTRG2 Input External trigger input pin for starting A D conversion 3 AD3 AN12 to AN15 Input Analog input pins ADTRG2 Input External trigger input pin for starting A D conversion ADTRG3 Input External trigger input pin for starting A D conversion Common AVCC Input Analo...

Page 781: ... A D data register D ADDRD 0000h 0008 8066h 16 A D control status register ADCSR x0h 0008 8070h 8 A D control register ADCR 00h 0008 8071h 8 ADDRy format select register ADDPR 00h 0008 8072h 8 A D sampling state register ADSSTR 19h 0008 8073h 8 2 AD2 A D data register A ADDRA 0000h 0008 8080h 16 A D data register B ADDRB 0000h 0008 8082h 16 A D data register C ADDRC 0000h 0008 8084h 16 A D data re...

Page 782: ...AD2 ADDRA 0008 8080h AD2 ADDRB 0008 8082h AD2 ADDRC 0008 8084h AD2 ADDRD 0008 8086h AD3 ADDRA 0008 80A0h AD3 ADDRB 0008 80A2h AD3 ADDRC 0008 80A4h AD3 ADDRD 0008 80A6h ADDRy registers are 16 bit read only registers which store an A D conversion result for each channel Table 23 5 lists the analog input channels and corresponding ADDRy registers 10 bit data can be relocated by setting the DPSEL bit ...

Page 783: ... than above are prohibited Unit 1 b3 b0 0 0 0 0 AN4 0 0 0 1 AN5 0 0 1 0 AN6 0 0 1 1 AN7 Settings other than above are prohibited b3 b0 0 0 0 0 AN4 0 0 0 1 AN4 and AN5 0 0 1 0 AN4 to AN6 0 0 1 1 AN4 to AN7 Settings other than above are prohibited Unit 2 b3 b0 0 0 0 0 AN8 0 0 0 1 AN9 0 0 1 0 AN10 0 0 1 1 AN11 Settings other than above are prohibited b3 b0 0 0 0 0 AN8 0 0 0 1 AN8 and AN9 0 0 1 0 AN8 ...

Page 784: ... operations CH 3 0 Bits Channel Select These bits select analog input channels that allow A D conversion Single mode ADCR MODE 1 0 bits 00b Select the single analog input channel that allows A D Scan mode ADCR MODE 1 0 bits 10b or 11b Select analog input channels up to 4 that allow A D conversion ADST Bit A D Start The ADST bit starts stops A D conversion Before setting the ADST bit to 1 complete ...

Page 785: ...read as 0 The write value should always be 0 R W b7 to b5 TRGS 2 0 Trigger Select Unit Trigger signal R W Unit 0 b7 b6 b5 0 0 0 Software trigger 0 0 1 Compare match input capture A signals from TPU0 to TPU5 0 1 0 Compare match A signal from TMR0 0 1 1 Trigger from ADTRG0 1 0 0 Compare match input capture A signal from TPU0 1 0 1 Compare match input capture A signals from TPU6 to TPU11 1 1 0 Settin...

Page 786: ...1 0 1 Compare match input capture A signals from TPU6 to TPU11 1 1 0 Setting prohibited 1 1 1 Trigger from ADTRG2 Note To start the A D conversion by the ADTRGn n 0 to 3 pin the Pm DDR Bj bit should be set to 0 input port and the Pm ICR Bj m 1 or 7 j 0 3 4 or 7 bit should be set to 1 input buffer for the corresponding pin is valid For details see section 14 I O Ports ADCR enables setting for an A ...

Page 787: ...ct The DPSEL bit selects whether data in the A D data registers is padded at the LSB or MSB end 23 2 5 A D Sampling State Register ADSSTR b7 b6 b5 b4 b3 b2 b1 b0 Value after reset 0 0 0 1 1 0 0 1 Addresses AD0 ADSSTR 0008 8053h AD1 ADSSTR 0008 8073h AD2 ADSSTR 0008 8093h AD3 ADSSTR 0008 80B3h ADSSTR is an 8 bit readable writable register that is used to set the sampling time for analog inputs Samp...

Page 788: ...ode In single mode A D conversion is to be performed for only once on the analog input of the specified single channel as below 1 A D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 A D conversion start by software TPU TMR or an external trigger input 2 When A D conversion is completed the A D conversion result is stored into the corresponding A D data registe...

Page 789: ...1 1 2 3 Store Interrupt generation 4 A D conversion result 1 Set A D conversion 2 Interrupt generation Set A D conversion 3 2 Clear 5 A D conversion result 2 Notes 1 indicates an instruction execution by software 2 Data during conversion is ignored Standby for conversion Standby for conversion Standby for conversion Standby for conversion Standby for conversion Standby for conversion Figure 23 5 E...

Page 790: ... on the first channel in the specified channel group 2 When A D conversion for each channel is completed the A D conversion result is stored into the corresponding A D data registers ADDRy 3 When A D conversion of all selected channels is completed if the ADIE bit in ADCSR is set to 1 A D interrupt enable by completing A D conversion an ADI interrupt request is generated A D converter starts A D c...

Page 791: ...tandby for conversion Interrupt generation Standby for conversion Clear 4 Standby for conversion Notes 1 indicates an instruction execution by software 2 Data during conversion is ignored A D conversion 3 A D conversion 4 A D conversion result 1 Standby for conversion Standby for conversion A D conversion result 2 A D conversion result 3 A D conversion result 4 A D conversion time Execute A D conv...

Page 792: ...t is generated 4 The ADST bit remains at 1 A D conversion start during A D conversion and is automatically cleared to 0 when A D conversion of all selected channels end The A D converter enters a wait state Figure 23 7 shows an example of A D conversion when three channels AN4 to AN6 are selected for analog input Set ADCSR ADST A D conversion start Channel 4 AN4 Standby for conversion Channel 5 AN...

Page 793: ... time is insufficient or the peripheral module clock PCLK is running at low speed the sampling time can be adjusted by using the ADSSTR The successive conversion time tSAM is fixed at 25 states of ADCLK Table 23 6 lists the sample of ADSSTR settings and table 23 7 lists the A D conversion time Legend tD tSPL tCONV Sampling signal ADI tD tSPL tSAM Successive conversion time A D conversion start del...

Page 794: ...es 1 A D conversion time in single mode and scan mode first round 2 A D conversion time in scan mode after the second round 1 2 3 2 3 The examples of the calculation of A D conversion times are listed below When PCLK ADCLK 50 MHz ADSSTR 19h and the conversion is the second round in scan mode A D conversion time tCONV ADSSTR ADCLK 25 ADCLK 25 50 MHz 25 50 MHz 0 5 μs 0 5 μs 1 0 μs When PCLK ADCLK 40...

Page 795: ...tarting A D conversion by two units synchronized unit activation Simultaneous activation of units 0 and 1 by a falling edge of the ADTRG0 signal is specified by setting the AD0 ADCR TRGS 2 0 bits to 011b specifying ADTRG0 as the trigger for unit 0 and the AD1 ADCR TRGS 2 0 bits to 111b specifying ADTRG0 as the trigger for unit 1 Simultaneous activation of units 2 and 3 by a falling edge of the ADT...

Page 796: ...t capture B signal from TPU0 setting the AD2 ADCR TRGS 2 0 bits to 100b specifying the compare match input capture C signal from TPU0 and setting the AD3 ADCR TRGS 2 0 bits to 100b specifying the compare match input capture D signal from TPU0 set up the compare match input capture A to D signals from TPU0 as the triggers that start conversion by units 0 to 3 AD0 ADCR TRGS 2 0 A D conversion start ...

Page 797: ... n 0 to 3 to 001b specifying the compare match input capture A signals from TPU0 to TPU5 and setting the TTGE bits in the TIERs of TPU0 and TPU2 to 1 set up the compare match input capture A signals from TPU0 and TPU2 as the triggers that start simultaneous conversion by units 0 to 3 AD0 ADCR TRGS 2 0 A D conversion start trigger A D converter unit 0 TPU unit 0 Compare match input capture A signal...

Page 798: ... two converter units Setting the ADn ADCR TRGS 2 0 bits n 0 1 to 010b specifying the compare match A signal from TMR0 and setting the ADTE bit in TCSR of TMR0 to 1 set up the compare match A signal from TMR0 as the trigger that starts simultaneous conversion by units 0 and 1 AD0 ADCR TRGS 2 0 A D conversion start trigger A D converter unit 0 TMR unit 0 Compare match A signal TMR0 TMR0 TCSR ADTE AD...

Page 799: ...ible 23 5 A D Conversion Accuracy Definitions This LSI s A D conversion accuracy definitions are given below Resolution The number of A D converter digital output codes Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 23 13 Offset error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output chan...

Page 800: ...1 1024 2 1024 1022 1024 1023 1024 Analog input voltage Ideal A D conversion characteristic Figure 23 13 A D Conversion Accuracy Definitions 1 FS Offset error Nonlinearity error Digital output Full scale error Ideal A D conversion characteristic Actual A D conversion characteristic Analog input voltage Figure 23 14 A D Conversion Accuracy Definitions 2 ...

Page 801: ...to the A D converter by clearing the ADST bit in ADCSR to 0 requires one cycle of the ADCLK If A D conversion is to be restarted right after the ADST bit was set to 0 set the ADST bit to 1 allow A D conversion to restart after one clock cycle has elapsed 23 6 4 Notes on Entering Power Down States When this LSI enters the module stop state or software standby mode with A D conversion enabled the an...

Page 802: ...example greater than 5 mV μs become impossible to track figure 23 15 Include a low impedance buffer if high rate analog signals are to be converted or conversion is to be in scan mode This LSI Equivalent circuit for the A D converter Cs Rs Figure 23 15 Equivalent Circuit for the Internal Circuit of Analog Input Pins Table 23 9 Specifications of Analog Pins Item Min Max Unit Permissible signal sour...

Page 803: ...re not in use ensure that VREFH AVcc Vcc and VREFL AVss Vss by making the same connections Range for the setting of VREFH Keep the reference voltage on the VREFH pin within the range defined by VREFH AVcc VCC AVCC AVSS VREFH VSS 0 1 µF 0 1 µF VREFL 0 1 µF Figure 23 16 Example of Connection for Power Supply Pins 23 6 8 Point for Caution Regarding Board Design As far as possible separate the analog ...

Page 804: ...excessively large surges connect capacitors as shown in figure 23 17 between AVcc and AVss and between VREFH and VREFL also connect suitable protective circuits to the analog input pins AN0 to AN15 Rin 2 AVCC VREFH AN0 to AN15 AVSS 1 1 VREFL 0 1 µF 0 1 µF The value in parentheses indicates the pin number 1 The value is for reference 2 Rin Input impedance Notes 10 µF 0 01 µF Figure 23 17 Example of...

Page 805: ...erter from affecting the conversion time the externally connected capacitors must be fully charged before the start of conversion Furthermore when the voltages on the analog input pins fluctuate due to scanning and so on so describing renewal of the charge of the externally connected capacitors high speed conversion is not realized Rin 2 AVCC VREFH AN0 to AN15 AVSS 1 1 VREFL 0 1 µF 0 1 µF 0 1 µF T...

Page 806: ...U or activation by compare match from TMR and match the conversion start timing and end timing of each unit Figure 23 19 shows timing example 1 when the conversion timings of four units are simultaneous Figure 23 20 shows timing example 2 when the conversion timings of four units are simultaneous Unit 0 ADCLK Unit 1 Unit 2 Unit 3 Successive approximation time Successive approximation time Successi...

Page 807: ...possible Possible 5 Activation by compare match A of TMR2 3 010b Impossible Impossible Possible Notes 1 Set the same value to TGRA to TGRD 2 The compare match A that is to be input to each unit of A D converter should be set for the same TPU channel 3 Units 0 and 1 of A D converter become compare match A of TMR0 and units 2 and 3 of that become compare match A of TMR2 For details on activation met...

Page 808: ... D A converter Table 24 1 Specifications of D A Converter Item Specifications Resolution 10 bits Output channels Two channels Power down function Module stop state can be set for each unit Module data bus Internal data bus 10 bit D A Control circuit Legend DADR0 DADR1 DACR DADPR Bus interface DACR DADR1 DADPR D A data register 0 D A data register 1 D A control register DADRy format select register...

Page 809: ...iguration of D A Converter Pin Name I O Function AVCC Input Analog circuit power supply pin AVSS Input Analog circuit ground pin VREFH Input D A converter reference power supply pin VREFL Input D A converter reference ground pin Connect this pin to the analog reference power supply 0 V DA0 Output Channel 0 analog output pin DA1 Output Channel 1 analog output pin ...

Page 810: ...1 b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5 DADPR DPSEL bit 0 Data padded at the LSB end Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADPR DPSEL bit 1 Data padded at the MSB end b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5 Addresses 0008 80C0h DADR1 0008 80C2h DADRy registers are 16 bit readable writable registers which s...

Page 811: ...s j 7 6 for pins used as analog outputs and the corresponding P6 ICR Bj bits j 7 6 to 0 For details see section 14 I O ports Table 24 4 Controls of D A Conversion b5 b7 b6 Description DAE DAOE1 DAOE0 0 0 0 D A conversion is disabled 1 D A conversion of channel 0 is enabled D A conversion of channel 1 is disabled Analog output of channel 0 DA0 is enabled Analog output of channel 1 DA1 is disabled 1...

Page 812: ... 0 D A conversion is independently controlled on channels 0 and 1 When the DAE bit is 1 D A conversion on channels 0 and 1 is controlled as a single whole The DAOE0 and DAOE1 bits control output of the results of conversion DAOE0 Bit D A Output Enable 0 The DAOE0 bit controls the D A conversion and analog output DAOE1 Bit D A Output Enable 1 The DAOE1 bit controls the D A conversion and analog out...

Page 813: ...Bit Name Description R W b6 to b0 Reserved These bits are always read as 0 The write value should always be 0 R W b7 DPSEL DADRy Format Select 0 D A data register is padded at the LSB end 1 D A data register is padded at the MSB end R W DADPR selects the placement of data in the D A data registers DPSEL Bit DADRy Format Select The DPSEL bit selects whether data in the D A data registers is padded ...

Page 814: ...t from the analog output pin DA0 after the conversion time tDCCONV has elapsed The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0 The output value is expressed by the following formula Setting value of DADR0 1024 VREFH 3 If DADR0 is written to again the conversion is immediately started The conversion result is output after the conversion ...

Page 815: ...D A Converter Simultaneously Because the A D converter and the D A converter of the RX610 Group use the same power supply conversion accuracy of A D conversion result may get affected depending on the usage The conversion accuracy is likely to be affected in the following cases If the D A data register DADR of D A converter is rewritten while the A D converter is being operated If the D A control ...

Page 816: ...0h Second period of rewriting 200h 10 0000 0000b Difference before and after rewriting 100h Third period of rewriting 300h 11 0000 0000b Difference before and after rewriting 100h Fourth period of rewriting 3FFh 11 1111 1111b Difference before and after rewriting 0FFh After changing 3FFh 11 1111 1111b A D converter One conversion period VREFH VREFL DADR 000h 100h 200h 300h 3FFh Figure 24 3 Example...

Page 817: ...or not the supply of internal power to RAM0 continues in deep software standby mode is selectable by the RAMCUTn bit n 2 to 0 in DPSBYCR If continuation of the supply of internal power is selected data in RAM0 are retained during periods in deep software standby mode The supply of internal power supply to RAM1 is halted at this time so data are not retained in RAM 1 See section 8 Low Power Consump...

Page 818: ... the ROM is possible while the data flash memory is being programmed or erased Suspension and resumption The CPU is able to execute program code from the ROM during suspension of programming or erasure Programming and erasure of the ROM can be restarted resumed after suspension Units of programming and erasure Unit of programming for the user mat and user boot mat 256 bytes Units of erasure for th...

Page 819: ...duct has different ROM sizes Product Code ROM Size ROM Addresses R5F56108 2 Mbytes FFE0 0000h to FFFF FFFFh R5F56107 1 5 Mbytes FFE8 0000h to FFFF FFFFh R5F56106 1 Mbyte FFF0 0000h to FFFF FFFFh R5F56104 768 Kbytes FFF4 0000h to FFFF FFFFh 2 Cannot be used in a product whose ROM size is equal to or smaller than 1 Mbyte ...

Page 820: ... register FCPSR FCU processing switching register DFLBCCNT Data flash blank check control register DFLBCSTAT Data flash blank check status register PCKAR Peripheral clock notification register FIFERR Flash interface error interrupt FRDYI Flash ready interrupt Peripheral bus FCURAME FSTATR0 FSTATR1 FENTRYR FRESETR FCMDR FRDY E FRDYI CPU Memory interface FCU RAM ROM mat User mat Up to 2 Mbytes User ...

Page 821: ... C402h 8 Flash access status register FASTAT 00h 007F C410h 8 Flash access error interrupt enable register FAEINT 9Bh 007F C411h 8 Flash ready interrupt enable register FRDYIE 00h 007F C412h 8 FCU RAM enable register FCURAME 0000h 007F C454h 16 Flash status register 0 FSTATR0 80h 007F FFB0h 8 Flash status register 1 FSTATR1 0xh 007F FFB1h 8 Flash P E mode entry register FENTRYR 0000h 007F FFB2h 16...

Page 822: ...it read mode 1 Register Read Method Register read mode is set to read a lock bit of ROM using the lock bit read 2 command R W b7 to b5 Reserved These bits are always read as 0 The write value should always be 0 R W FMODR is a register to specify the method for the reading of lock bits When on chip ROM is disabled the data read from FMODR is 00h and writing is disabled FMODR is initialized by a res...

Page 823: ...locked state R b6 b5 Reserved These bits are always read as 0 The write value should always be 0 R W b7 ROMAE ROM Access Violation 0 No ROM access error 1 ROM access error R W Note Only 0 can be written after reading 1 to clear the flag FASTAT is a register to check if the access to the ROM data flash is allowed When on chip ROM is disabled the data read from FASTAT is 00h and writing is disabled ...

Page 824: ...ENTRY1 bit is set to 1 A read command is issued for ROM programming erasure addresses 00F0 0000h to 00FF FFFFh when the FCU is in ROM P E normal mode and the FENTRYR FENTRY0 bit is set to 1 A command is issued for ROM programming erasure addresses 00E0 0000h to 00EF FFFFh when the FENTRY1 bit is set to 0 A command is issued for ROM programming erasure addresses 00F0 0000h to 00FF FFFFh when the FE...

Page 825: ... FIFERR interrupt requests disabled when the CMDLK bit in FASTAT is set to 1 1 FIFERR interrupt requests enabled when the CMDLK bit in FASTAT is set to 1 R W b6 b5 Reserved These bits are always read as 0 The write value should always be 0 R W b7 ROMAEIE ROM Access Violation Interrupt Enable 0 FIFERR interrupt requests disabled when the ROMAE bit in FASTAT is set to 1 1 FIFERR interrupt requests e...

Page 826: ...writing of the FCRME bit R W Note Write data is not retained FCURAME is a register to enable and disable an access to the FCU RAM area Only specific values written to the upper byte in word access are valid Data written to the upper byte is not retained When on chip ROM is disabled the data read from FCURAME is 00h and writing is disabled FCURAME is initialized by a reset FCRME Bit FCU RAM Enable ...

Page 827: ...ogramming R b5 ERSERR Erasure Error 0 Erasure terminates normally 1 An error occurs during erasure R b6 ILGLERR Illegal Command Error 0 FCU detects no illegal command or ROM data flash access 1 FCU detects an illegal command or ROM data flash access R b7 FRDY Flash Ready 0 During programming erasure During suspending programming erasure During the lock bit read 2 command processing During the blan...

Page 828: ...command During programming erasure process the FCU enters the command locked state PRGERR Bit Programming Error This bit is used to indicate the result of the ROM data flash programming process by the FCU When the PRGERR bit is set to 1 the FCU is placed in the command locked state see section 26 8 2 Error Protection Setting condition An error occurs during programming A programming command is iss...

Page 829: ...he FCU is placed in the command locked state see section 26 8 2 Error Protection Setting conditions The FCU detects an illegal command The FCU detects an illegal ROM data flash access one of the ROMAE DFLAE DFLRPE and DFLWPE bits in FASTAT is 1 The setting of FENTRYR is invalid Clearing condition After the FCU processes a status clear command under conditions where FASTAT is set to 10h FRDY Bit Fl...

Page 830: ... occurs in the FCU processing R FSTATR1 is a register to check the FCU status When on chip ROM is disabled the data read from FSTATR1 is 00h FSTATR1 is initialized by a reset or when the FRESET bit in FRESETR is set to 1 FLOCKST Bit Lock Bit Status This bit is to reflect the read data of a lock bit when using the lock bit read 2 command When the FRDY bit in FSTATR0 is set to 1 after a lock bit rea...

Page 831: ... b7 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W FRDYIE is a register to enable and disable the flash ready interrupt FRDYI output When on chip ROM is disabled the data read from FRDYIE is 00h and writing is disabled FRDYIE is initialized by a reset FRDYIE Bit Flash Ready Interrupt Enable This bit is to enable disable a FRDYI interrupt request when programm...

Page 832: ...ing erasing 00F0 0000h to 00FF FFFFh ROM more than 1 Mbyte Address for reading FFE0 0000h to FFEF FFFFh Address for writing erasing 00E0 0000h to 00EF FFFFh 2 Cannot be used in a product whose ROM size is equal to or smaller than 1 Mbyte 3 Write data is not retained FENTRYR is a register to place the ROM data flash in P E mode To place the ROM data flash in P E mode so that the FCU can accept comm...

Page 833: ...TRY0 bit When the writing enable conditions are met and FENTRYR is other than 0000h data is written to FENTRYR FENTRY1 Bit ROM P E Mode Entry 1 This bit is used to place 1 Mbyte of ROM read addresses FFE0 0000h to FFEF FFFFh programming erasure addresses 00E0 0000h to 00EF FFFFh in P E mode Writing enable conditions when all of the following conditions are met On chip ROM is enabled The FRDY bit i...

Page 834: ...0 0000h to FFFF FFFFh 1 1 Do not set R5F56107 1 5 Mbytes 0 0 ROM read mode Read addresses FFE8 0000h to FFFF FFFFh 0 1 ROM P E mode Programming erasure addresses 00F0 0000h to 00FF FFFFh Access disabled addresses FFE8 0000h to FFFF FFFFh 1 0 Programming erasure addresses 00E8 0000h to 00EF FFFFh Access disabled addresses FFE8 0000h to FFFF FFFFh 1 1 Do not set R5F56106 1 Mbyte Unusable 2 0 ROM rea...

Page 835: ... specific values written to the upper byte in word access are valid Any other writing causes the register to be initialized Data written to the upper byte is not retained When on chip ROM is disabled the data read from FPROTR is 0000h and writing is disabled FPROTR is initialized by a reset or when the FRESET bit in FRESETR is set to 1 FPROTCN Bit Lock Bit Protection Cancel This bit is used to ena...

Page 836: ...tained When on chip ROM is disabled the data read from FRESETR is 0000h and writing is disabled FRESETR is initialized by a reset FRESET Bit Flash Reset When the FRESET bit is set to 1 programming erasure operations for the ROM data flash are forcibly terminated and the FCU is initialized High voltage is applied to the memory of the ROM data flash during programming erasure To ensure time required...

Page 837: ... from FCMDR is 0000h and writing is disabled FCMDR is initialized by a reset or when the FRESET bit in FRESETR is set to 1 Table 26 5 lists the states of FCMDR after receiving each command For details on the blank check processing see section 27 6 Programming and Erasing the Data Flash Memory Table 26 5 States of FCMDR after Receiving Each Command Command CMDR PCMDR Normal mode transition FFh Prev...

Page 838: ...e 1 Erasure priority mode R W b15 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W FCPSR is a register to select the method of suspending the FCU erasure processing When on chip ROM is disabled the data read from FCPSR is 0000h and writing is disabled FCPSR is initialized by a reset or when the FRESET bit in FRESETR is set to 1 ESUSPMD Bit Erasure Suspend Mode ...

Page 839: ...than the lock bit protection Values other than above are reserved R b15 to b8 Reserved These bits are always read as 0 and cannot be modified R FPESTAT is a register to indicate the result of the programming erasure processing for the ROM data flash When on chip ROM is disabled the data read from FPESTAT is 0000h and writing is disabled FPESTAT is initialized by a reset or when the FRESET bit in F...

Page 840: ... in FRESETR is set to 1 PCKA 7 0 Bits Peripheral Clock Notification These bits are used to set the peripheral clock PCLK at the programming erasure for the ROM data flash Set the PCKA 7 0 bits to the PCLK frequency and issue a peripheral clock notification command before programming erasure Do not change the frequency during the programming erasure processing for the ROM data flash Calculate the s...

Page 841: ...te Erase b1 and b0 0 0 Write erase disabled 0 1 Write erase enabled 1 0 Write erase disabled initial value 1 1 Write erase disabled R W b7 to b2 Reserved These bits are always read as 0 The write value should always be 0 R W FWEPROR is a readable writable register to protect the execution of the flash write erase with software FWEPROR is initialized in software standby mode or deep software standb...

Page 842: ... 0000h 2 Mbytes R5F56107 FFE8 0000h 1 5 Mbytes R5F56106 FFF0 0000h 1 Mbyte R5F56104 FFF4 0000h 768 Kbytes Programming Erasure Address 00E0 0000h 00E8 0000h 00F0 0000h 00F4 0000h Address FFE0 0000h Address FFFF FFFFh User mat 2 Mbytes For reading Address 00E0 0000h Address 00FF FFFFh For programming erasure For reading User boot mat 16 Kbytes Address FF7F C000h Address FF7F FFFFh Figure 26 2 Memory...

Page 843: ...ocks Erasure Blocks R5F56108 FFE0 0000h 11 EB17 to EB27 R5F56107 FFE8 0000h 7 EB17 to EB23 R5F56106 FFF0 0000h 3 EB17 to EB19 R5F56104 FFF4 0000h 1 EB17 Figure 26 3 Configuration of Erasure Blocks for the User Mat 26 5 Operating Modes Associated with the ROM Figure 26 4 is a diagram of the operating mode transitions for the RX610 Group On release from the reset state transitions are in accord with...

Page 844: ... Mode can shift ROME 0 EXBE 0 ROME 0 EXBE 1 ROME 0 Note Initial value after a reset ROME 0 EXBE 0 EXBE 1 On chip ROM disabled expansion mode On chip ROM Disabled External bus Enabled ROME 0 EXBE 1 On chip ROM enabled expansion mode On chip ROM Enabled External bus Enabled ROME 1 EXBE 1 On chip ROM Enabled External bus Disabled ROME 1 EXBE 0 On chip ROM Disabled External bus Disabled ROME 0 EXBE 0 ...

Page 845: ...programming Programmable and erasable mat User mat User boot mat User mat User mat Division into erasure blocks Possible 1 Possible Poss ble Target mat for booting after a reset Mat containing the embedded program 2 User boot mat User mat Notes 1 The entire ROM may be erased at the time of booting up Specified blocks can subsequently be erased For details refer to section 26 10 2 ID Code Protectio...

Page 846: ...with on chip ROM enabled and to on chip ROM enabled expansion mode 26 6 1 FCU Modes The FCU has five modes or sets of modes Transitions between modes are caused by modifying FENTRYR or issuing FCU commands Figure 26 5 is a diagram of the FCU mode transitions ROM P E mode ROM status read mode B A ROM P E normal mode ROM lock bit read mode C B A C Data flash P E mode ROM data flash read mode FENTRYR...

Page 847: ... causes a ROM access violation and the FCU enters the command locked state see section 26 8 2 Error Protection ROM P E normal mode ROM status read mode and ROM lock bit read mode are the three ROM P E modes 1 ROM P E Normal Mode The transition to ROM P E normal mode is the first transition in the process of programming or erasing the ROM The FCU enters this mode when the FENTRYD bit in FENTRYR is ...

Page 848: ... bit read mode see section 26 6 3 Connections between FCU Modes and Commands Peripheral clock notification Sets the frequency of the peripheral clock Programming ROM programming in 256 byte units Block erasure ROM erasure in block units with the lock bit being erased simultaneously P E suspension Suspends programming erasure P E resumption Resumes programming erasure Status register clearing Clear...

Page 849: ... WDn RA WDn RA WDn RA D0h Block erasure 2 RA 20h BA D0h P E suspension 1 RA B0h P E resump ion 1 RA D0h Status register clearing 1 RA 50h Lock bit read 2 2 RA 71h BA D0h Lock bit programming 2 RA 77h BA D0h Legend Address column RA ROM programming erasure address When the FENTRY0 bit in FENTRYR is 1 An address from 00F0 0000h to 00FF FFFFh When the FENTRY1 bit in FENTRYR is 1 An address from 00E0 ...

Page 850: ...TR1 Table 26 9 Acceptable Commands and the State and Mode ROM P E Mode of the FCU P E Normal Mode Status Read Mode Lock Bit Read Mode Programming suspended Erasure suspended Other state Programming or erasure Processing to suspend programming or erasure Lock bit read 2 processing Programming suspended Erasure suspended Command locked state Other state Programming suspended Erasure suspended Other ...

Page 851: ...es a transition to ROM P E mode for programming and erasure of the corresponding address range Before actually proceeding to program or erase the ROM enable programming and erasure by writing 01h as a byte to FWEPROR see section 26 2 15 Flash Write Erase Protection Register FWEPROR Write to FENTRYR Set ROM P E mode When setting the FENTRY1 bit to 1 Write AA02h When setting the FENTRY0 bit to 1 Wri...

Page 852: ...Wait tRESW2 Issue a status register clear command Write AA00h to FENTRYR Timeout tE128K 10h Yes No Yes No FCU initialization ILGLERR 0 ERSERR 0 PRGERR 0 End Start Note tE128K Erasure time for a 128 Kbyte erasure block see section 29 Electrical Characteristics tRESW2 Reset pulse width during programming erasure see section 29 Electrical Characteristics 0 1 Write 02h to FWEPROR Read from FENTRYR 000...

Page 853: ...8 Procedure for Transition to ROM P E Normal Mode 4 Switching to ROM Status Read Mode Issuing an FCU command other than a normal mode transition or lock bit read mode transition command places the FCU in ROM status read mode The same transition can be obtained by issuing the status read mode transition command Figure 26 9 shows the procedure for checking the register FSTATR0 as an example In the e...

Page 854: ...ll bits of a value thus read out have the value of the lock bit of the erasure block that contains the accessed address figure 26 10 Transition to ROM lock bit read mode Check the transition to ROM lock bit read mode Read the value of the lock bit Use the address for ROM programming and erasure Do not use the address for reading Start End Write 71h to the address for ROM programming and erasure in...

Page 855: ...a status clear command Issue an FCU command 1 Error check Error No error Determine the error source and issue a status clear command Check the execution result of the FCU command 2 NG OK Transferred only one time after reset is cleared For details see section 26 6 4 2 1 Transferring Firmware to the FCU RAM Set FWEPROR and FENTRYR Issued only one time after a peripheral clock is set For details see...

Page 856: ...an 0000h 0000h FENTRYR check Write C401h to FCURAME Copy to FCU RAM Clear the FENTRY1 and FENTRY0 bits See section 26 6 4 1 2 Switching to ROM Read Mode Enable access to the FCU RAM Copy the FCU firmware to the FCU RAM Transfer source FEFF E000h to FEFF FFFFh FCU firmware area Transfer destination 007F 8000h to 007F 9FFFh FCU RAM area Start End Figure 26 12 Procedure for Firmware Transfer to FCU R...

Page 857: ... has been written three times as a word to the address range for programming and erasure of the ROM the process of the FCU setting the frequency of the peripheral clock starts once the value D0h has been written as a byte in the sixth cycle The FRDY bit in FSTATR0 can be used to check whether or not the settings have been completed Addresses that can be used in the first to sixth cycles differ acc...

Page 858: ...ccess n 3 Write D0h to ROM programming erasure address in byte access FRDY bit check Timeout tPCKA 1 FCU initialization FRESETR FRESET 1 writing ILGLERR bit check Wait tRESW2 2 FRESETR FRESET 0 writing Notes 1 tPCKA 60 µs when PCLK 50 MHz 120 µs when PCLK 25 MHz 2 tRESW2 Reset pulse width during programming erasure see section 29 Electrical Characteristics No Yes No Yes 0 1 Set PCKAR to frequency ...

Page 859: ...nd erasure of the ROM in the 131st cycle the FCU begins the actual process of programming the ROM The FRDY bit in FSTATR0 can be used to check whether or not the programming has been completed Addresses that can be used in the first to 131st cycles differ according to the settings of the FENTRY0 and FENTRY1 bits in FENTRYR Ensure that the addresses suit the settings of these bits If issuing of the...

Page 860: ...amming data to ROM programming erasure address in word access n 127 Write D0h to ROM programming erasure address in byte access FRDY bit check Timeout tP256 1 1 FCU initialization FRESETR FRESET 1 writing ILGLERR bit and PRGERR bit check Wait tRESW2 FRESETR FRESET 0 writing Note tP256 Programming time for 256 byte data see section 29 Electrical Characteristics tRESW2 Reset pulse width during progr...

Page 861: ... FSTATR0 To execute an erasure with lock bit protection disabled set the FPROTCN bit in FPROTR before erasure Write 20h to ROM programming erasure address in byte access Write D0h to arbitrary address in erasure block in byte access FRDY bit check Time out tE128K 1 1 FCU initialization FRESETR FRESET 1 writing ILGLERR bit and ERSERR bit check Wait tRESW2 FRESETR FRESET 0 writing Note tE128K Erasur...

Page 862: ...e address in byte access Write D0h to arbitrary address in erasure block in byte access FRDY bit check Timeout tP256 1 1 FCU initialization FRESETR FRESET 1 writing ILGLERR bit and PRGERR bit check Wait tRESW2 FRESETR FRESET 0 writing Note tP256 Programming time for 256 byte data see section 29 Electrical Characteristics tRESW2 Reset pulse width during programming erasure see section 29 Electrical...

Page 863: ... the FLOCKST bit in FSTATR1 In the case of the memory area reading method i e when the FRDMD bit in FMODR is 0 the FCU is placed in lock bit reading mode and the lock bit is obtained by reading from an address within the address range for programming and erasure of the ROM Details are given in section 26 6 4 1 5 Switching to ROM Lock Bit Read Mode FRDY bit check Write D0h to arbitrary address in e...

Page 864: ...aring Flash Status Register 0 FSTATR0 To clear the ILGLERR ERSERR and PRGERR bits in FSTATR0 use the status register clear command When one of the ILGLERR ERSERR and PRGERR bits in FSTATR0 is 1 the FCU is placed in the command locked state and receives no FCU commands other than the status register clear command If the ILGLERR is 1 also check the values of the ROMAE DFLAE DFLRPE and DFLWPE bits in...

Page 865: ...re at least one of the ILGLERR PRGERR ERSERR and FCUERR bits is set to 1 When programming erasure processing has finished during the interval from when it is checked that the SUSRDY bit is 1 to when a P E suspend command is received the ILGLERR bit is set to 1 because the issued P E suspend command is detected as an illegal command When programming erasure processing has finished simultaneously wi...

Page 866: ... to ROM programming erasure address in byte access ERSSPD bit and PRGSPD bit check Timeout tSEED 1 1 FCU initialization FRESETR FRESET 1 writing Wait tRESW2 FRESETR FRESET 0 writing No Yes FCUERR bit check Timeout tE128K FRDY bit check ILGLERR bit check 10h Issue a status register clear command Read FASTAT Write 10h to FASTAT No Yes LGLERR ERSERR PRGERR FCUERR 1 FCUERR 0 ILGLERR 0 ERSERR 0 PRGERR ...

Page 867: ...mand is issued and then issue a P E resume command FRDY bit check Write D0h to ROM programming erasure address in byte access FRESETR FRESET 1 writing Wait tRESW2 FRESETR FRESET 0 writing FCU initialization No Yes ILGLERR bit ERSERR bit and PRGERR bit check Timeout tE128K 1 1 0 1 Note tE128K Erasure time for a 128 Kbyte erasure block see section 29 Electrical Characteristics tRESW2 Reset pulse wid...

Page 868: ...ters the state in which the P E suspend command can be received after starting programming the SUSRDY bit in FSTATR0 is set to 1 When a P E suspend command is issued the FCU receives the command and clears the SUSRDY bit to 0 If the FCU receives a P E suspend command while a programming pulse is being applied the FCU continues applying the pulse After specified pulse application time the FCU finis...

Page 869: ...affects the control method of erasure pulses In suspension priority mode when receiving a P E suspend command while erasure pulse A that has never been suspended in the past is being applied the FCU suspends the application of erasure pulse A and enters the erasure suspended state When receiving a P E suspend command while reapplying erasure pulse A after erasure is resumed by a P E resume command...

Page 870: ...rocessing If the FCU receives a P E suspend command while an erasure pulse is being applied the FCU definitely continues applying the pulse In this mode required time for the whole erasure processing can be reduced as compared with the suspension priority mode because the reapplication of erasure pulses does not occur when a P E resume command issued Pulse A application continues Legend E Erasure ...

Page 871: ... 1 When the lock bit protection is violated and a ROM programming erasure related command is issued the FCU detects a programming erasure error and enters the command locked state see section 26 8 2 Error Protection 26 8 2 Error Protection With the error protection FCU command issuance errors prohibited access occurrences and FCU malfunctions are detected and an FCU command is prohibited from bein...

Page 872: ... an erasure suspend target area in the erasure suspended state 1 0 0 0 0 1 Other than 80h is specified in the second cycle of the programming command 1 0 0 0 0 1 A command is issued in the command locked state 1 0 1 0 1 0 1 0 1 1 Erasure error An error occurs during erasure 0 1 0 0 0 1 When the FPROTCN bit in FPROTR is 0 a block erase command is issued to a erasure block whose lock bit is set to 0...

Page 873: ...de the host sends control commands and data for programming and the user mat user boot mat and data mat are programmed or erased accordingly An on chip SCI handles transfer between the host and RX610 in asynchronous mode Tools for the transmission of control commands and the data for programming must be prepared in the host When the RX610 is activated in boot mode the program on the mat that holds...

Page 874: ...abled only when the two match The control code and ID code in the ROM consists of four 32 bit words Figure 26 25 shows the configuration of the control code and ID code The ID code should be set in 32 bit units Control code ID code 1 ID code 2 ID code 3 ID code 4 ID code 5 ID code 6 ID code 7 ID code 8 ID code 9 ID code 10 ID code 11 ID code 12 ID code 13 ID code 14 ID code 15 FFFF FFA0h FFFF FFA4...

Page 875: ...n to the state of waiting for a host command Non matching ID code Further transition to the ID code protection waiting state 50h 72h 6Fh 74h 65h 63h 74h FFh FFh Protection enabled authentication method 3 Always judged to be a non matching ID code Other than the above Protection disabled Erasure of all blocks 2 ID Code The ID code can be set to any desired value However if the control code is 52h a...

Page 876: ...on command Programming select command End of programming 1 ID code protected Protection enabled ID OK Failed Retry Failed The number for retrying is overflowed 5 Wait for inquiry selec ion host command Wait for the ID code Check the ID code Execute inquiry selection host command Bit rate adjustment Wait for programming erasure host command Execute host command read or check Wait for data for progr...

Page 877: ...e two match If they do not match the next transition is back to the state of waiting for an ID code However if the ID codes fail to match three times in a row and also the state of protection is authentication method 1 the ROM is completely erased and the state of waiting for an ID code is entered again A reset is required to release the system from this state due to non matching ID codes For deta...

Page 878: ...ly and then sends a 00h byte to the host If reception of the value 00h by the host is normal the host responds by sending the value 55h to the RX610 If normal reception of 00h by the host is not possible the RX610 is re booted in boot mode and then repeats the process of automatically adjusting the bit rate If reception of the value 55h by the RX610 is normal it responds by sending E6h to the host...

Page 879: ... the number of user boot mats and the start and end addresses User mat information inquiry Inquires regarding the number of user mats and the start and end addresses Erasure block information inquiry Inquires regarding the number of blocks and the start and end addresses Programming size inquiry Inquires regarding the size of programming data New bit rate selection Modifies the bit rate of SCI com...

Page 880: ...Operating frequency inquiry New bit rate selection Inquiry regarding mat programming information Programming erasure state transition End Figure 26 29 Example of Procedure to Use Inquiry Selection Host Commands for User Mat User Boot Mat Each host command is described in detail below The command in the description indicates a command sent from the host to the RX610 and the response indicates a res...

Page 881: ...e selected device Command 20h Response 30h Size Device count Character count Device code Product code Character count Device code Product code Character count Device code Product code SUM Legend Size 1 byte Total number of bytes in the device count character count device code and product code fields Device count 1 byte Number of device types supported by the embedded program for boot mode Characte...

Page 882: ...d 10h Size Device code SUM Response 06h Error response 90h Error Legend Size 1 byte Number of characters in the device code field fixed at four Device code 4 bytes ASCII code for the product name of the chip one of the device codes returned in response to the supported device inquiry command SUM 1 byte Checksum Error 1 byte Error code 11h Checksum error illegal command 21h Incorrect device code er...

Page 883: ... 91h Be sure to issue a clock mode selection command only after issuing a device selection command Even when 00h or 01h has been returned as the number of supported clock modes in response to a clock mode inquiry command issue a clock mode selection command to specify the clock mode that has been returned as the result of the inquiry Command 11h Size Mode SUM Response 06h Error response 91h Error ...

Page 884: ...tio Multiplication ratio count Multiplication ratio Multiplication ratio Multiplication ratio SUM Legend Size 1 byte Total number of bytes in the clock type count multiplication ratio type and multiplication ratio fields Clock type count 1 byte Number of clock types for example 02h indicates two clock types that is a system clock and a peripheral clock Multiplication ratio count 1 byte Number of s...

Page 885: ...ency Maximum frequency SUM Legend Size 1 byte Total number of bytes in the clock type count minimum frequency and maximum frequency fields Clock type count 1 byte Number of clock types for example 02h indicates two clock types that is a system clock and a peripheral clock Minimum frequency 2 bytes Minimum value of the operating frequency for example 07D0h indicates 20 00 MHz This value should be c...

Page 886: ...mmand 24h Response 34h Size Area count Area start address Area end address Area start address Area end address Area start address Area end address SUM Legend Size 1 byte Total number of bytes in the area count area start address and area end address fields Area count 1 byte Number of user boot mat areas consecutive areas are counted as one area Area start address 4 bytes Start address of a user bo...

Page 887: ...mmand 25h Response 35h Size Area count Area start address Area end address Area start address Area end address Area start address Area end address SUM Legend Size 1 byte Total number of bytes in the area count area start address and area end address fields Area count 1 byte Number of user mat areas consecutive areas are counted as one area Area start address 4 bytes Start address of a user mat are...

Page 888: ...SUM Legend Size 1 byte Total number of bytes in the block count block start address and block end address fields Block count 1 byte Number of erasure blocks in the user mat Block start address 4 bytes Start address of an erasure block Block end address 4 bytes End address of an erasure block SUM 1 byte Checksum 10 Programming Size Inquiry In response to a programming size inquiry command sent from...

Page 889: ...its for a one bit period in the previous bit rate with which the new bit rate selection command has been sent and then sets the host s bit rate to the new one After that the host sends confirmation data 06h in the new bit rate and the RX610 returns a response 06h to the confirmation data Be sure to issue a new bit rate selection command only after a clock mode selection command Host RX610 New bit ...

Page 890: ...n by 2 Multiplication ratio 2 1 byte Multiplication division ratio of the input frequency to obtain the peripheral clock PCLK This value is represented in the same format as multiplication ratio 1 SUM 1 byte Checksum Error Error code 11h Checksum error 24h Bit rate selection error 25h Input frequency error 26h Multiplication ratio error 27h Operating frequency error Bit rate selection error A bit ...

Page 891: ...nimum and maximum operating frequencies for each clock issue an operating clock frequency inquiry command 12 Programming Erasure State Transition In response to a programming erasure state transition command sent from the host the RX610 determines whether ID code protection is enabled or disabled using the control code and ID code written in the ROM When ID code protection is enabled the RX610 ret...

Page 892: ...s Code Code Description 11h Waiting for device selection 12h Waiting for clock mode selection 13h Waiting for bit rate selection 1Fh Waiting for transition to programming erasure host command wait state bit rate has been selected 31h Erasing the user mat and user boot mat 3Fh Waiting for a programming erasure host command 4Fh Waiting for reception of programming data 5Fh Waiting for erasure block ...

Page 893: ...d Wait State 1 ID Code Check In response to an ID code check command sent from the host the RX610 compares the code sent from the host with the control code and ID code in the ROM and returns the result Command 60h Size Control code ID code SUM Response ACK Error response E0h Error Legend Size 1 byte Number of bytes in the ID code field fixed at 16 ID code 16 bytes Control code 1 byte ID code 15 b...

Page 894: ...t an undefined command the RX610 returns a response indicating a command error For the format of this response see section 26 10 5 Inquiry Selection Host Command Wait State To program the ROM issue a programming selection command user boot mat programming selection or user mat programming selection command and then a 256 byte programming command from the host Upon reception of a programming select...

Page 895: ...rasure Block erasure End Block specification Block specification Block number FFh specification Figure 26 32 Procedure for ROM Erasure in Boot Mode Each host command is described in detail below The command in the description indicates a command sent from the host to the RX610 and the response indicates a response sent from the RX610 to the host The checksum is byte size data calculated so that th...

Page 896: ...occurred during ROM programming the RX610 returns an error response D0h Command 50h Programming address Data Data Data SUM Response 06h Error response D0h Error Legend Programming address 4 bytes Target address of programming To program the ROM a 256 byte boundary address should be specified To terminate programming FFFF FFFFh should be specified Data 256 bytes Programming data FFh should be speci...

Page 897: ...the ROM After completing ROM erasure successfully the RX610 returns a response 06h If an error has occurred during ROM erasure the RX610 returns an error response D8h Command 58h Size Block SUM Response 06h Error response D8h Error Legend Size 1 byte Number of bytes in the block specification field fixed at 1 Block 1 byte Block number whose data is to be erased To terminate erasure FFh should be s...

Page 898: ...nse D2h Error Legend Size 1 byte Total number of bytes in the area read start address and reading size fields Area 1 byte Target mat to be read 00h User boot mat 01h User mat Read start address 4 bytes Start address of the area to be read Reading size 4 bytes Size of data to be read bytes SUM 1 byte Checksum Data 1 byte Data read from the ROM Error 1 byte Error code 11h Checksum error 2Ah Address ...

Page 899: ... user mat data in byte units and returns the result checksum Command 4Bh Response 5Bh Size Mat checksum SUM Legend Size 1 byte Number of bytes in the mat checksum field fixed at 4 Mat checksum 4 bytes Checksum of the user mat data The user mat also stores the key code for debugging function authentication Note that the checksum includes this key code value SUM 1 byte Checksum for the response data...

Page 900: ... the RX610 has failed to read the lock bit the RX610 returns an error response F1h Command 71h Size Area Third highest order address Second highest order address Highest order address SUM Response Status Error response F1h Error Legend Size 1 byte Total number of bytes in the area third highest order address second highest order address and highest order address fields fixed at 4 in the RX610 Area...

Page 901: ...d highest order address second highest order address and highest order address fields fixed at 4 in the RX610 Area 1 byte Target mat to be locked 01h User mat Third highest order address 1 byte Third highest order address at the specified block s end address 8 to 15 bits Second highest order address 1 byte Second highest order address at the specified block s end address 16 to 23 bits Highest orde...

Page 902: ...age 902 of 1006 Feb 20 2013 14 Lock Bit Disable In response to a lock bit disable command sent from the host the RX610 disables a lock bit Command 75h Response 06h 15 Embedded Program Status Inquiry For details refer to section 26 10 5 Inquiry Selection Host Command Wait State ...

Page 903: ...f matching and the ID code is always considered to be non matching Furthermore if all bytes of the control code and ID code have the value FFh there is no determination of matching the ID code is always considered to match and connection of the on chip debugger is allowed See figure 26 25 for the configuration of ID codes in flash memory Table 26 18 Specifications for ID Code Protection on Connect...

Page 904: ... erasure block 00 in boot mode or by user programming FFFF FF9Ch 31 0 ROM code Figure 26 33 Configuration of a ROM Code Table 26 19 Specifications for ROM Code Protection ROM Code State of Protection Operations at the Time of Connection with the PROM Programmer 0000 0000h Protection enabled ROM code protection 1 Access both reading and writing to the user mat and user boot mat is prohibited 0000 0...

Page 905: ...bit in FRESETR is used to reset the FCU make sure that the reset state is maintained over the period tRESW2 see section 29 Electrical Characteristics Do not attempt to read a target ROM for programming or erasure during the period of an FCU reset A WDT reset however can be applied even during programming or erasure regardless of the time to be secured that was described above 5 Prohibition of Non ...

Page 906: ...the power supply voltage of RX610 to go outside the specified range for operation Do not change the value of the FWEPROR FLWE 1 0 bits Do not change the operating mode by changing the setting of the SYSCR0 ROME bit Do not change the multiplication ratio of PCLK by using the SCKCR register Do not change the frequency of PCLK by changing the setting of the PCKAR register Do not make a transition to ...

Page 907: ...m the ROM is possible while the data flash memory is being programmed or erased Suspension and resumption The CPU is able to execute program code from the ROM during suspension of programming or erasure Programming and erasure of the ROM can be restarted resumed after suspension Units of programming and erasure Unit of programming for the data mat 8 or 128 bytes Unit of erasure for the data mat 8 ...

Page 908: ...R FCU process switch register DFLBCCNT Data flash blank check control register DFLBCSTAT Data flash blank check status register PCKAR Peripheral clock notification register FIFERR Flash interface error interrupt FRDYI Flash ready interrupt Peripheral bus FCURAME FSTATR0 FSTATR1 FENTRYR FRESETR FCMDR FRDYIE FRDYI CPU Memory interface FCU RAM ROM mat unit User mat Up to 2 Mbytes User boot mat 16 Kby...

Page 909: ...FMODR 00h 007F C402h 8 Flash access status register FASTAT 00h 007F C410h 8 Flash access error interrupt enable register FAEINT 9Bh 007F C411h 8 Flash ready interrupt enable register FRDYIE 00h 007F C412h 8 Data flash read enable register DFLRE 0000h 007F C440h 16 Data flash programming erasure enable register DFLWE 0000h 007F C450h 16 FCU RAM enable register FCURAME 0000h 007F C454h 16 Flash stat...

Page 910: ...en placed in lock bit read mode 1 Register Reading Method This is the setting when the blank checking command is to be used R W b7 to b5 Reserved These bits are always read as 0 The write value should always be 0 R W FMODR is used to specify the method for the reading of lock bits Set the FRDMD bit to 1 if blank checking is to be used In modes in which the on chip ROM is disabled the value read fr...

Page 911: ... Reserved This bit is always read as 0 The write value should always be 0 R W b3 DFLAE Data Flash Access Violation 0 No data flash access violation 1 Data flash access violation R W b4 CMDLK FCU Command Lock 0 FCU is not in the command locked state 1 FCU is in the command locked state R b6 b5 Reserved These bits are always read as 0 The write value should always be 0 R W b7 ROMAE ROM Access Violat...

Page 912: ...ing 1 DFLAE Bit Data Flash Read Protection Violation This bit indicates whether a data flash access violation occurred When the DFLAE bit is set to 1 the ILGLERR bit in FSTATR0 is set to 1 placing the FCU in the command locked state For FSTATR0 see section 26 2 5 Flash Status Register 0 FSTATR0 Setting conditions A read command is issued for a data flash area in data flash P E normal mode and when...

Page 913: ...FLAE bit in FASTAT is set to 1 1 FIFERR interrupt requests enabled when the DFLAE bit in FASTAT is set to 1 R W b4 CMDLKIE FCU Command Lock Interrupt Enable 0 FIFERR interrupt requests disabled when the CMDLK bit in FASTAT is set to 1 1 FIFERR interrupt requests enabled when the CMDLK bit in FASTAT is set to 1 R W b6 b5 Reserved These bits are always read as 0 The write value should always be 0 R ...

Page 914: ...tion Interrupt Enable This bit is used to enable or disable FIFERR interrupt requests when a data flash access violation occurs and the DFLAE bit in FASTAT is set to 1 CMDLKIE Bit FCU Command Lock Interrupt Enable This bit is used to enable or disable FIFERR interrupt requests when a FCU command locked state occurs and the CMDLK bit in FASTAT is set to 1 ...

Page 915: ... 7 0 Key Code Enable or disable rewriting of the DBREj bit j 3 to 0 R W Note Write data is not retained DFLRE is a register to enable or disable the DB0 to DB3 blocks see figure 27 3 to be read Only specific values written to the upper byte in word access are valid Data written to the upper byte is not retained When on chip ROM is disabled the data read from DFLRE is 0000h and writing is disabled ...

Page 916: ...0 R W b15 to b8 KEY 7 0 Key Code Enable or disable rewriting of the DBWEj bit j 3 to 0 R W Note Write data is not retained DFLWE is a register to enable or disable the DB0 to DB3 blocks see figure 27 3 to be programmed or erased Only specific values written to the upper byte in word access are valid Data written to the upper byte is not retained When on chip ROM is disabled the data read from DFLW...

Page 917: ...E mode R W b15 to b8 FEKEY 7 0 Key Code Enable or disable rewriting of the FENTRYD FENTRY1 and FENTRY0 bits R W Note Write data is not retained FENTRYR is a register to place the ROM data flash in P E mode To place ROM data flash in P E mode and accept commands from the FCU one of the FENTRYD FENTRY1 and FENTRY0 bits must be set to 1 If more than one bit is set to 1 the ILGLERR bit is set in FSTAT...

Page 918: ... access Setting condition When the writing enable conditions are met FENTRYR is set to 0000h and 1 is written to the FENTRYD bit Clearing conditions Data is written in byte access Data is written in word access when the FEKEY 7 0 bits are other than AAh When the writing enable conditions are met 0 is written to the FENTRYD bit When the writing enable conditions are met and FENTRYR is other than 00...

Page 919: ...alue should always be 0 R W DFLBCCNT is a register for specifying the address and size of the area to be checked by a blank check command When on chip ROM is disabled the data read from DFLBCCNT is 0000h and writing is disabled DFLBCCNT is initialized by a reset or when the FRESET bit in FRESETR is set to 1 For FRESETR see section 26 2 10 Flash Reset Register FRESETR BCSIZE Bit Blank Check Size Se...

Page 920: ...e area to be blank checked is erased blank 1 0 or 1 is written in the area to be blank checked R b15 to b1 Reserved These bits are always read as 0 The write value should always be 0 R W DFLBCSTAT is a register which stores the results of a blank check command When on chip ROM is disabled the data read from DFLBCSTAT is 0000h and writing is disabled DFLBCSTAT is initialized by a reset or when the ...

Page 921: ...ss 0010 7FFFh Data mat 32 Kbytes Figure 27 2 Configuration of the Data Mat 27 4 Block Configuration The configuration of erasure blocks for the data mat is shown in figure 27 3 As units of erasure the data mat is divided into 4 blocks of 8 Kbytes Programming is in 8 or 128 byte units Programming in eight byte units proceeds for the eight bytes from an address for which the three lower order bits a...

Page 922: ...programming and erasure On board programming On board programming On board programming Programmable and erasable mat Data mat Data mat Data mat Division into erasure blocks Poss ble 1 Possible Possible Target mat for booting after a reset Mat containing the embedded program 2 User boot mat User mat Notes 1 All flash memory areas may be erased at the time of booting up Specified blocks can subseque...

Page 923: ...d single chip mode with on chip ROM enabled and to on chip ROM enabled expansion mode 27 6 1 FCU Modes The FCU has five modes or sets of modes Transitions between modes are caused by writing to FENTRYR or issuing FCU commands Figure 27 4 is a diagram of the FCU mode transitions Data flash P E mode Data flash status read mode B A Data flash P E normal mode Data flash lock bit read mode C B A C ROM ...

Page 924: ...ds in this mode Read access to an address within the data flash area causes a data flash access violation and the FCU enters the command locked state High speed reading of the ROM is possible 2 Data Flash Status Read Mode The data flash status read mode is for reading information on the state of the data flash The FCU enters this mode when a command other than the normal mode transition and lock b...

Page 925: ...s been erased is blank Commands other than the blank checking command are also for use with the ROM The blank checking command for the data flash memory is also used as the lock bit read 2 command for the ROM That is when the same command is issued for the ROM a lock bit of the ROM is read out Commands for the FCU are issued by write access to addresses within the data flash area Table 27 6 shows ...

Page 926: ... and the FCUERR bit in FSTATR1 Table 27 7 Acceptable Commands and the State and Mode Data Flash P E Mode of the FCU P E Normal Mode Status read mode Lock bit read mode Programming suspended Erasure suspended Other state Programming or erasure Processing to suspend programming or erasure Blank checking Programming suspended Erasure suspended Command locked state Other state Programming suspended Er...

Page 927: ...ogramming command and the number of words N to be programmed in the second cycle Access the peripheral bus in words from the third cycle to cycle N 2 of the command In the third cycle write the first word of data for programming to the address where the target area for programming starts This address must be on an 8 byte boundary for 8 byte programming or on a 128 byte boundary address for 128 byt...

Page 928: ... data word to a data flash area n N 1 Write byte D0h to a data flash area address Timeout tP128 1 1 FCU initialization Check the ILGLERR and PRGERR bits Note tP128 Time required for programming 128 byte data see section 29 Electrical Characteristics tRESW2 Reset pulse width during programming erasure see section 29 Electrical Characteristics No Yes No Yes 0 1 Start End 8 byte programming N 04h 128...

Page 929: ...FRDMD bit in FMODR to 1 to enable the command and then specify the size and start address of the target area in DFLBCCNT If the BCSIZE bit of DFLBCCNT is set to 1 checking will be performed for the entire erasure block 8 Kbytes specified in the second cycle of the command If the BCSIZE bit is set to 0 checking will be performed on the 8 byte range starting from the address obtained by adding the s...

Page 930: ...Time required for blank check of 8 Kbyte data see section 29 Electrical Characteristics tRESW2 Reset pulse width during programming erasure see section 29 Electrical Characteristics No Yes 0 1 Start End BCSIZE 0 8 bytes 1 8 Kbytes BCADR The address of a target area when BCSIZE 0 Write 71h to the addresses in data flash area in byte units Check DFLBCSTAT FRDY bit check FRESETR FRESET 1 writing FRES...

Page 931: ...lash read mode is selected Since the FCU does not accept commands in ROM data flash read mode data flash programming and erasure are disabled If an attempt is made to issue an FCU command for the data flash in ROM data flash read mode the FCU detects an illegal command error and enters the command locked state see section 27 7 2 Error Protection 3 Protection through DFLWE When the DBWEj j 3 to 0 b...

Page 932: ...tion types used in common by the ROM and data flash FENTRYR setting error most illegal command errors erasing errors programming errors and FCU errors see section 26 8 2 Error Protection If the FCU enters the command locked state due to a command other than a suspension command issued during programming or erasure processing the FCU continues programming or erasing the data flash In this state the...

Page 933: ...ection Host Command Wait State Table 27 9 Inquiry Selection Host Commands only for Data Flash Host Command Name Function Data mat inquiry Inquires regarding the availability of data mat Data mat information inquiry Inquires regarding the number of data mats and the start and end addresses Each host command is described in detail below The command in the description indicates a command sent from th...

Page 934: ...end address Area start address Area end address SUM Legend Size 1 byte Total number of bytes in the area count area start address and area end address fields Area count 1 byte Number of data mat areas consecutive areas are counted as one area Area start address 4 bytes Start address of a data mat area Area end address 4 bytes End address of a data mat area SUM 1 byte Checksum The information conce...

Page 935: ... mat programming selection user boot mat programming selection 256 byte programming erasure selection block erasure and memory read commands refer to section 26 10 7 Programming Erasing Host Command Wait State For the erasure block information inquiry command refer to section 26 10 5 Inquiry Selection Host Command Wait State Table 27 10 Programming Erasure Host Commands only for Data Flash Host Co...

Page 936: ...t As the initial values of DFLRE and DFLWE are 0000h programming erasure and reading of the data mat are disabled immediately after a reset To read data from the data mat set DFLRE appropriately before accessing the data mat To program or erase the data mat set DFLWE appropriately before issuing an FCU command for programming or erasure If an attempt is made to read program or erase the data mat w...

Page 937: ...ck diagram of the boundary scan function Table 28 1 Specifications of Boundary Scan Item Description Boundary scan enabled disabled Boundary can is enabled when the EMLE pin is driven low and the BSCANP pin is driven high Dedicated boundary scan pins Pins P02 P03 P04 P05 and WDTOVF are dedicated for JTAG when boundary scan function is enabled Six test modes BYPASS mode EXTEST mode SAMPLE PRELOAD m...

Page 938: ...on register JTIR 4h 4 Bypass register JTBPR Undefinded 1 Boundary scan register JTBSR Undefinded IDCODE register JTIDR 0809 9447h 32 Instructions can be input to the instruction register JTIR via the test data input pin TDI by serial transfer The bypass register JTBPR which is a 1 bit register is connected between the TDI and TDO pins in BYPASS mode The boundary scan register JTBSR which is a JTBS...

Page 939: ...TIR by serial input from the TDI pin JTIR is initialized when the TRST signal is low level when the TAP controller is in the Test Logic Reset state 28 2 2 Bypass Register JTBPR JTBPR is a 1 bit register and is connected between the TDI and TDO pins when JTIR is set to BYPASS mode JTBPR cannot be read from or written to by the CPU 28 2 3 Boundary Scan Register JTBSR JTBSR is a shift register to con...

Page 940: ...ble Output 399 398 397 F4 MDE Input 396 F1 MD1 Input 395 F2 MD0 Input 394 G4 P86 Input Output enable Output 393 392 391 G3 P85 Input Output enable Output 390 389 388 H2 NMI Input 387 J4 P34 Input Output enable Output 386 385 384 J3 PF6 Input Output enable Output 383 382 381 J1 PF5 Input Output enable Output 380 379 378 J2 PF4 Input Output enable Output 377 376 375 K4 P33 Input Output enable Output...

Page 941: ...utput enable Output 344 343 342 N2 P24 Input Output enable Output 341 340 339 P1 P23 Input Output enable Output 338 337 336 P2 P22 Input Output enable Output 335 334 333 R1 P21 Input Output enable Output 332 331 330 N3 P20 Input Output enable Output 329 328 327 R2 P17 Input Output enable Output 326 325 324 N4 P16 Input Output enable Output 323 322 321 P4 P15 Input Output enable Output 320 319 318 ...

Page 942: ...put enable Output 290 289 288 N7 P56 Input Output enable Output 287 286 285 R7 P55 Input Output enable Output 284 283 282 P7 P54 Input Output enable Output 281 280 279 M8 P83 Input Output enable Output 278 277 276 R8 P82 Input Output enable Output 275 274 273 M9 P81 Input Output enable Output 272 271 270 N9 P80 Input Output enable Output 269 268 267 R9 P53 Input Output enable Output 266 265 264 P9...

Page 943: ...ut enable Output 236 235 234 R13 P75 Input Output enable Output 233 232 231 M12 PC7 Input Output enable Output 230 229 228 P13 PC6 Input Output enable Output 227 226 225 R14 PC5 Input Output enable Output 224 223 222 P14 PC4 Input Output enable Output 221 220 219 R15 PC3 Input Output enable Output 218 217 216 N13 PH2 Input Output enable Output 215 214 213 N14 PC2 Input Output enable Output 212 211...

Page 944: ...ut enable Output 182 181 180 K14 P73 Input Output enable Output 179 178 177 J12 P72 Input Output enable Output 176 175 174 J13 P71 Input Output enable Output 173 172 171 J15 P70 Input Output enable Output 170 169 168 H12 PB0 Input Output enable Output 167 166 165 H15 PH1 Input Output enable Output 164 163 162 H14 PH0 Input Output enable Output 161 160 159 G12 PA7 Input Output enable Output 158 157...

Page 945: ... Output enable Output 128 127 126 D14 PE7 Input Output enable Output 125 124 123 D13 PE6 Input Output enable Output 122 121 120 C15 PE5 Input Output enable Output 119 118 117 D12 PE4 Input Output enable Output 116 115 114 C14 PE3 Input Output enable Output 113 112 111 B15 PE2 Input Output enable Output 110 109 108 B14 PE1 Input Output enable Output 107 106 105 A15 PE0 Input Output enable Output 10...

Page 946: ...0 PD3 Input Output enable Output 74 73 72 C10 PD2 Input Output enable Output 71 70 69 A10 PD1 Input Output enable Output 68 67 66 B10 PD0 Input Output enable Output 65 64 63 D9 PG4 Input Output enable Output 62 61 60 C9 PG3 Input Output enable Output 59 58 57 A9 PG2 Input Output enable Output 56 55 54 B9 PG1 Input Output enable Output 53 52 51 D8 PG0 Input Output enable Output 50 49 48 A8 P97 Inpu...

Page 947: ...30 D6 P91 Input Output enable Output 29 28 27 A6 P90 Input Output enable Output 26 25 24 C5 P47 Input Output enable Output 23 22 21 A5 P46 Input Output enable Output 20 19 18 B5 P45 Input Output enable Output 17 16 15 D5 P44 Input Output enable Output 14 13 12 A4 P43 Input Output enable Output 11 10 9 B4 P42 Input Output enable Output 8 7 6 C4 P41 Input Output enable Output 5 4 3 D4 P40 Input Outp...

Page 948: ...2 b21 b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5 Value after reset 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 Value after reset 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 Bit Description R W b31 to b0 JTID is a register with the fixed value that indicates the device IDCODE JTID is a 32 bit register JTID data is output from the TDO pin when the IDCODE instruction has been executed ...

Page 949: ...P pin is driven high 28 3 1 TAP Controller Figure 28 2 shows the state transition diagram of the TAP controller Test logic reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR Run test idle 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR 0 0 1 0 0 0 1 0 1 1 1 0 Figure 28 2 State Transition of TAP Controller ...

Page 950: ... and reload the data to the scan path While this instruction is executed input signals are directly input to the LSI and output signals are also directly output to the external circuits The LSI system circuit is not affected by this instruction In SAMPLE operation the boundary scan register latches the snap shot of data transferred from input pins to internal circuit or data transferred from inter...

Page 951: ...can register is maintained regardless of the TAP controller state BYPASS is connected between TDI and TDO the same operation as BYPASS instruction can be achieved 6 HIGHZ Instruction Code 0111b When the HIGHZ instruction is selected all output pins enter high impedance state While the HIGHZ instruction is selected the status of boundary scan register is maintained regardless of the state of the TA...

Page 952: ...s LSI are in the following states 1 Reset state 2 Hardware standby mode software standby mode and deep software standby mode 8 While the pin with the open drain function is enabled set the output scan register to 1 and the output enable register to 1 by the boundary scan function In this case executing any of EXTEST CLAMP and SAMPLE PRELOAD instructions makes the pin high output instead of high im...

Page 953: ...o P97 Output enable Output signal Output signal RIIC output RIIC input signal 1 Configuration of ICC pins P14 to P17 Open drain buffer for RIIC Boundary scan cell Boundary scan cell Boundary scan cell P14 to P17 Output enable Output signal Input signal DA output 3 Configuration of D A pins P66 and P67 Analog buffer P66 and P67 Boundary scan cell Boundary scan cell Output enable Output signal Analo...

Page 954: ...ge VREFH 0 3 to VCC 0 3 V Analog power supply voltage AVCC 2 0 3 to 4 6 V Analog input voltage VAN 0 3 to VCC 0 3 V Operating temperature Topr Regular specifications 20 to 85 C Wide range specifications 40 to 85 Storage temperature Tstg 55 to 125 C Caution Permanent damage to the LSI may result if absolute maximum ratings are exceeded Notes 1 Ports 0 and 14 to 17 are 5 V tolerant 2 Connect AVCC to...

Page 955: ...ports 2 to E 144 pin LQFP ports 2 to H 176 pin LFBGA Other input pins VIH VCC x 0 8 VCC 0 3 VIL 0 3 VCC x 0 2 Input high voltage except Schmitt trigger input pin MD pin EMLE VIH VCC x 0 9 VCC 0 3 V EXTAL VCC x 0 8 VCC 0 3 D0 to D15 VCC x 0 7 VCC 0 3 Input low voltage except Schmitt trigger input pin MD pin EMLE VIL 0 3 VCC x 0 1 V EXTAL 0 3 VCC x 0 2 D0 to D15 0 3 VCC x 0 3 Output high voltage All...

Page 956: ...ring D A conversion per unit 0 4 0 6 Idle all units 0 3 1 0 μA RAM standby voltage VRAM 2 5 V VCC start voltage 9 VCCSTART 0 8 V VCC rising gradient 9 SVCC 20 ms V Notes 1 This does not include the pins which are multiplexed as ports 0 and 14 to 17 for 5 V tolerant 2 This includes the multiplexed pins but RIIC input pins for ports 14 to 17 are excluded 3 Supply current values are with all output p...

Page 957: ...pins ICFER FMPE 0 IOL 6 0 mA RIIC pins ICFER FMPE 1 IOL 20 0 mA Permissible output low current max value per pin All output pins except for RIIC pins IOL 4 0 mA RIIC pins ICFER FMPE 0 IOL 6 0 mA RIIC pins ICFER FMPE 1 IOL 20 0 mA Permissible output low current total Total of all output pins ΣIOL 80 mA Permissible output high current average value per pin All output pins IOH 2 0 mA Permissible outp...

Page 958: ...5 C wide range specifications Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 125 ns Figure 29 1 Clock high pulse width tCH 15 ns Clock low pulse width tCL 15 ns Clock rising time tCr 5 ns Clock falling time tCf 5 ns Oscillation settling time after reset crystal tOSC1 10 ms Figure 29 4 Oscillation settling time after leaving software standby mode crystal tOSC2 10 ms Figure 29 2 O...

Page 959: ...Feb 20 2013 Software standby mode power down mode IRQ exception handling IRQMD 1 0 10b SSBY 1 WAIT instruction Oscillation settling time tOSC2 IRQ exception handling 01 10 SSBY SSIER SSIi IRQMD 1 0 IRQ ICLK Oscillator Figure 29 2 Oscillation Settling Timing after Software Standby Mode ...

Page 960: ...eption handling Oscillation settling time tOSC3 Wait instruction Cleared When IOKEEP L Operating When IOKEEP H Oscillator ICLK IRQ IRQ interrupt Set DIRQnF set request Set DIRQnEG bit Set DPSBY bit Cleared Set IOKEEP bit Cleared Set L L I O port Operating Retained IOKEEP bit I O port Operating Retained Operating DPSRSTF flag Internal reset L H Undefined Figure 29 3 Oscillation Settling Timing afte...

Page 961: ...rical Characteristics R01UH0032EJ0120 Rev 1 20 Page 961 of 1006 Feb 20 2013 tOSC1 tDEXT VCC EXTAL RES ICLK Figure 29 4 Oscillation Settling Timing tEXf VCC x 0 5 EXTAL tEXH tEXL tEXr Figure 29 5 External Input Clock Timing ...

Page 962: ...ions RES pulse width except for ROM data flash programming erasure tRESW 1 20 tcyc Figure 29 6 1 5 µs Internal reset time during ROM data flash programming erasure tRESW2 2 35 µs NMI pulse width tNMIW 200 ns Figure 29 7 IRQ pulse width tIRQW 200 ns Figure 29 8 Notes 1 Both the time and the number of cycles should satisfy the specifications 2 This is to specify the FCU reset and the WDT reset RES t...

Page 963: ...itions VOH VCC x 0 5 VOL VCC x 0 5 IOH 1 0 mA IOL 1 0 mA C 30 pF Item Symbol Min Max Unit Test Conditions Address delay time tAD 30 ns Figures 29 9 to 29 12 Byte control delay time tBCD 30 ns CS delay time tCSD 30 ns RD delay time tRSD 20 ns RD setup time tRSS 0 5 1 BCLK 20 ns Read data setup time tRDS 15 ns Read data hold time tRDH 0 ns WR delay time tWRD 20 ns WR setup time tWRS 0 5 1 BCLK 20 ns...

Page 964: ... to A0 D15 to D0 Read Byte write strobe mode 1 write strobe mode BC1 BC0 Common to both byte write strobe mode and 1 write strobe mode tBCD tCSD tCSD RD Read tRSD tRSD tAD tRDH tRDS tAD tAD tBCD TW1 tRSS tRSS TW2 Tend Tn1 RDON 1 CSRWAIT 2 CSROFF 1 CSON 0 Th Figure 29 9 External Bus Timing Normal Read Cycle Bus Clock Synchronized ...

Page 965: ...e BC1 BC0 Common to both byte write strobe mode and 1 write strobe mode tBCD tCSD tCSD tAD tAD tAD tBCD Tw1 D15 to D0 Write WR0 WR1 WR Write tWRD tWRD tWDH tWDD tWRS tWRS Tw2 Tend Tn1 Th WRON 1 WDON 1 CSWWAIT 2 CSWOFF 1 WDOFF 1 CSON 0 Note Be sure to specify WDON and WDOFF as at least one cycle of BCLK Figure 29 10 External Bus Timing Normal Write Cycle Bus Clock Synchronized ...

Page 966: ...1 CSPRWAIT 2 RDON 1 CSPRWAIT 2 RDON 1 CSON 0 Figure 29 11 External Bus Timing Page Read Cycle Bus Clock Synchronized A23 to A1 CS7 to CS0 tAD BCLK A23 to A0 Byte write strobe mode 1 write strobe mode BC1 BC0 Common to both byte write strobe mode and 1 write strobe mode tBCD tCSD tCSD tAD tBCD TW1 D15 to D0 Write WR0 WR1 WR Write tWRD tWRD tWDH tWDD tWRS tWRS TW2 Tend Tpw1 Tpw2 tAD tAD tWRD tWRD tW...

Page 967: ...s R01UH0032EJ0120 Rev 1 20 Page 967 of 1006 Feb 20 2013 tWTS tWTH tWTS tWTH CSRWAIT 3 CSWWAIT 3 BCLK A23 to A0 CS7 to CS0 RD Read WR Write WAIT TW1 TW2 Tend Tend TW3 Tn1 Th External wait Figure 29 13 External Bus Timing External Wait Control ...

Page 968: ...CLK tcyc PPG Pulse output delay time tPOD 40 ns Figure 29 17 8 bit timer Timer output delay time tTMOD 40 ns Figure 29 18 Timer reset input setup time tTMRS 25 ns Figure 29 19 Timer clock input setup time tTMCS 25 ns Figure 29 20 Timer clock pulse width Single edge setting tTMCWH 1 5 x 1 PCLK tcyc Both edge setting tTMCWL 2 5 x 1 PCLK tcyc WDT Overflow output delay time tWOVD 40 ns Figure 29 21 SC...

Page 969: ...1000 ns Start condition input hold time tSTAH 3 5 x 1 PCLK 300 ns Re start condition input setup time tSTAS 5x 1 PCLK 1000 ns Stop condition input setup time tSTOS 3 5 x 1 PCLK 300 ns Data input setup time tSDAS 250 ns Data input hold time tSDAH 0 ns SCL SDA capacitive load Cb 400 pF RIIC Fast mode ICFER FMPE 0 SCL input cycle time tSCL 8 10 x 1 PCLK 600 ns SCL input high pulse width tSCLH 3 5 x 1...

Page 970: ...BUF 5 x 1 PCLK 120 ns Start condition input hold time tSTAH 3 5 x 1 PCLK 120 ns Re start condition input setup time tSTAS 5 x 1 PCLK 120 ns Stop condition input setup time tSTOS 3 5 x 1 PCLK 120 ns Data input setup time tSDAS 50 ns Data input hold time tSDAH 0 ns SCL SDA capacitive load Cb 550 pF Boundary scan 176 pin LFBGA TCK clock cycle time tTCKcyc 100 ns Figure 29 26 TCK clock high level puls...

Page 971: ...A Ports 0 to E write 144 pin LQFP Ports 0 to H write 177 pin LFBGA Figure 29 14 I O Port Input Output Timing Output compare output PCLK Input capture input Notes TIOCA0 to TIOCA11 TIOCB0 to TIOCB11 TIOCC0 TIOCC3 TIOCC6 TIOCC9 TIOCD0 TIOCD3 TIOCD6 TIOCD9 tTOCD tTICS Figure 29 15 TPU Input Output Timing PCLK TCLKA to TCLKH tTCKS tTCKS tTCKWL tTCKWH Figure 29 16 TPU Clock Input Timing ...

Page 972: ...eb 20 2013 PCLK PO31 to PO0 tPOD Figure 29 17 PPG Output Timing PCLK TMO0 to TMO3 tTMOD Figure 29 18 8 Bit Timer Output Timing PCLK TMRI0 to TMRI3 tTMRS Figure 29 19 8 Bit Timer Reset Input Timing PCLK TMCI0 to TMCI3 tTMCS tTMCS tTMCWL tTMCWH Figure 29 20 8 Bit Timer Clock Input Timing ...

Page 973: ...re 29 21 WDT Output Timing SCK0 to SCK6 tSCKW tSCKr tSCKf tScyc Figure 29 22 SCK Clock Input Timing tTXD tRXS tRXH SCK0 to SCK6 TxD0 to TxD6 Transmit data RxD0 to RxD6 Receive data Figure 29 23 SCI Input Output Timing Clock Synchronous Mode PCLK ADTRG0 to ADTRG3 tTRGS Figure 29 24 A D Converter External Trigger Input Timing ...

Page 974: ... conditions VIH VCC 0 7 VIL VCC 0 3 VOL 0 6V IOL 6mA ICFER FMPE 0 VOL 0 4V IOL 15mA ICFER FMPE 1 Sr Note S P and Sr represent the following conditions S Start condition P Stop condition Sr Retransmit start condition Figure 29 25 I2 C Bus Interface Input Output Timing TCK tTCKcyc tTCKH tTCKf tTCKL tTCKr Figure 29 26 Boundary Scan TCK Timing RES TRST TCK tTRSTW Figure 29 27 Boundary Scan TRST Timing...

Page 975: ...RX610 Group 29 Electrical Characteristics R01UH0032EJ0120 Rev 1 20 Page 975 of 1006 Feb 20 2013 tTMSS TCK TMS TDI TDO tTMSH tTDIS tTDIH tTDOD Figure 29 28 Boundary Scan Input Output Timing ...

Page 976: ...input capacitance 6 0 pF INL integral nonlinearity error INL 1 5 3 0 LSB Offset error 1 5 3 0 LSB Full scale error 1 5 3 0 LSB Quantization error 0 5 LSB Absolute accuracy 1 5 3 0 LSB DNL differential nonlinearity error DNL 0 5 1 0 LSB Notes 1 The conversion time includes the sampling time and the comparison time As the test conditions the number of sampling states is indicated 2 The scanning is n...

Page 977: ...end delay time during writing tSPD 120 µs Figure 29 29 PCLK 50 MHz First suspend delay time during erasing in suspend priority mode tSESD1 120 µs Second suspend delay time during erasing in suspend priority mode tSESD2 1 7 ms Suspend delay time during erasing in erasure priority mode tSEED 1 7 ms Data hold time 3 TDRP 10 Year Notes 1 Definition of rewrite erase cycle The rewrite erase cycle is the...

Page 978: ...ion First suspend delay time during erasing in suspend priority mode tDSESD1 120 µs Second suspend delay time during erasing in suspend priority mode tDSESD2 1 7 ms Suspend delay time during erasing in erasure priority mode tDSEED 1 7 ms Data hold time 3 TDDRP 10 Year Notes 1 Definition of rewrite erase cycle The rewrite erase cycle is the number of erasing for each block When the rewrite erase cy...

Page 979: ...e suspend in suspend priority mode FCU command FSTATR0 FRDY Erasure pulse Erasure suspend in erasure priority mode Program Suspend Ready Not Ready Ready Programming Erase Suspend Ready Not Ready Ready Erasing Erase Suspend Resume Suspend Ready Not Ready Ready Not Ready Erasing Erasing tSPD tDSPD tSESD1 tDSESD1 tSESD2 tDSESD2 tSEED tDSEED Figure 29 29 ROM Data Flash Write Erase Suspend Timing ...

Page 980: ...C A1 IRQ4 A All HiZ Keep O 1 Keep Keep HiZ P35 to P37 All HiZ Keep O Keep Keep HiZ Port 4 All HiZ Keep O 1 Keep Keep HiZ P50 WR0 WR Single chip mode EXBE 0 HiZ Keep O Keep Keep HiZ On chip ROM enabled disabled extended mode EXBE 1 WR0 WR output H WR0 WR output HiZ P51 WR1 BC1 Single chip mode EXBE 0 HiZ Keep O Keep Keep HiZ On chip ROM enabled disabled extended mode EXBE 1 WR1 WR output H WR1 WR o...

Page 981: ...utput HiZ Other than the above Keep O Keep Keep HiZ P62 CS2 A CS6 A All HiZ CS output H Other than the above Keep O CS output HiZ Other than the above Keep O Keep Keep HiZ P63 CS3 A CS7 A All HiZ CS output H Other than the above Keep O CS output HiZ Other than the above Keep O Keep Keep HiZ P64 CS4 B All HiZ CS output H Other than the above Keep O CS output HiZ Other than the above Keep O Keep Kee...

Page 982: ... than the above Keep O Keep Keep HiZ P72 to P75 All HiZ Keep O Keep Keep HiZ P76 RQ14 A All HiZ Keep O 1 Keep Keep HiZ P77 All HiZ Keep O Keep Keep HiZ Port 8 All HiZ Keep O Keep Keep HiZ Port 9 All HiZ Keep O Keep Keep HiZ Port A Single chip mode EXBE 0 HiZ Keep O Keep Keep HiZ On chip ROM enabled disabled extended mode EXBE 1 Address output Address output retained Other than the above HiZ Addres...

Page 983: ...xtended mode EXBE 1 Address output Address output retained Other than the above Keep O Address output HiZ Other than the above Keep O PC5 to PC7 Single chip mode EXBE 0 HiZ Keep O Keep Keep HiZ On chip ROM enabled disabled extended mode EXBE 1 Address output Address output retained CS output H Other than the above Keep O Address output HiZ CS output HiZ Other than the above Keep O Port D Single ch...

Page 984: ...s Keep O 1 16 bit bus HiZ Port F All HiZ Keep O Keep Keep HiZ Port G All HiZ Keep O Keep Keep HiZ Port H All HiZ Keep O Keep Keep HiZ WDTOVF All WDTOVF output H H H Legend H High level L Low level Keep O Output pins retain their previous values and input pins become high impedance 1 Input to pins in use as external interrupt pins and set up as triggers for release from software standby mode is pos...

Page 985: ...UH0032EJ0120 Rev 1 20 Page 985 of 1006 Feb 20 2013 Appendix 2 Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in Packages on Renesas Technology Corp website 176 pin LFBGA PLBG0176GA A ...

Page 986: ...0 0 19 9 E 1 4 A2 22 2 22 0 21 8 22 2 22 0 21 8 1 7 A 0 15 0 1 0 05 0 65 0 5 0 35 L x 8 0 c 0 5 e 0 10 y HD HE A1 bp b1 c1 ZD ZE L1 P LQFP144 20x20 0 50 1 2g MASS Typ 144P6Q A FP 144L FP 144LV PLQP0144KA A RENESAS Code JEITA Package Code Previous Code F 1 36 37 72 73 108 109 144 1 2 3 x Index mark y H E E D HD bp ZD Z E Detail F c A L A 1 A 2 L1 2 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH NOT...

Page 987: ...Standby Interrupt Flag Register DPSIFR Description added 8 5 2 1 Transitions to All Module Clock Stop Mode Note 5 added 8 5 3 1 Transition to Software Standby Mode Note 3 added Figure 8 4 Example of Flowchart to Use Deep Software Standby Mode changed 8 7 5 Input Buffer Control by DIRQiE Bit i 3 to 0 changed 193 193 197 to 199 203 205 206 207 208 209 210 212 215 216 216 216 221 221 222 10 Interrupt...

Page 988: ...ingle Request for Transfer changed Figure 11 11 Example of Normal Write Operation when Two Rounds of Bus Access are Generated in Response to a Single Request for Transfer changed 11 5 5 4 Point for Caution Regarding Register Settings added 285 12 DMA Controller DMAC Table 12 4 Setting of DCTG 5 0 Bits DMA Request Source changed for 100111b 101000b 101001b and 101010b on the DCTG 5 0 bit 338 13 Dat...

Page 989: ...Changed Figure 20 17 Example of Serial Reception Flowchart Clock Synchronous Mode changed 20 4 5 Simultaneous Serial Data Transmission and Reception Clock Synchronous Mode changed 618 623 627 629 631 634 Figure 20 18 Example of Simultaneous Serial Transmission Reception Flowchart Clock Synchronous Mode changed 20 5 5 Initialization of the SCI changed Figure 20 26 Sample Serial Transmission Flowcha...

Page 990: ...Signal Sources changed 23 6 7 Ranges of Settings for Analog Power Supply and Other Pins changed Figure 23 16 Example of Connections for AVcc Vcc and AVss Vss changed 23 6 9 Point for Caution Regarding Countermeasures for Noise changed Figure 23 17 Example of a Protective Circuit for Analog Inputs changed 23 6 10 Realizing High Speed Conversion changed Figure 23 18 Example of an Externally Connecte...

Page 991: ... in this section changed Table 27 1 Specifications of Data Flash Memory added Figure 27 1 Block Diagram of Data Flash Memory changed Table 27 2 Input and Output Pins Associated with the Data Flash changed 27 2 1 Flash Mode Register FMODR Table of bits Function on the FRDMD bit changed Description on the FRDMD bit changed 27 3 Configuration of Memory Mat for the Data Flash Memory added 27 4 Block C...

Page 992: ...iagram of the 144 Pin LQFP changed Table 1 3 List of Pins and Pin Functions changed Table 1 4 Pin Functions changed 44 45 51 to 54 55 59 65 68 74 78 Section 2 CPU 2 1 Features Register set of the CPU Accumulator changed Figure 2 1 Register Set of the CPU changed 2 2 2 8 Floating Point Status Word FPSW RM 1 0 Floating Point Rounding Mode Setting Bit name changed Bit description added 2 2 3 Accumula...

Page 993: ... Control Unit ICU 10 2 2 Interrupt Request Destination Setting Register n ISELRn Bit description list Notes 1 and 2 added 10 2 4 Interrupt Priority Register m IPRm bits IPR 2 0 Bit name changed Table 10 4 Interrupt Vector Table changed 10 6 2 Returning from Software Standby Mode added 251 253 254 257 259 to 262 263 to 266 287 287 290 Section 11 Buses Table 11 6 Registers of the External Bus Contro...

Page 994: ... 2 5 Timer Status Register TSR Bit allocation Value after a reset changed 15 2 8 Timer Start Register TSTRA TSTRB Bit allocation TSTRB address changed 15 2 9 Timer Synchronous Register TSYRA TSYRB Bit allocation TSYRB address changed 543 549 Section 17 8 Bit Timer TMR Table 17 3 Registers of TMR changed 17 2 6 Timer Control Status Register TCSR Bit allocation Value after a reset changed 566 569 Se...

Page 995: ...I2 C Bus Bit Rate High Level Register ICBRH Transfer rate expression changed Table 22 6 Examples of ICBRH ICBRL Settings for Transfer Rate changed Figure 22 5 Example of RIIC Initialization Flow changed 22 3 3 Master Transmitter Operation changed Figure 22 6 Example of Master Transmission Flowchart changed 22 3 4 Master Receiver Operation changed Figure 22 10 Example of Master Reception Flowchart ...

Page 996: ... Mbytes 2 Mbytes 1 5 Mbytes 1 Mbyte or 768 Kbytes changed Flash interface error name FCUERR FIFERR changed Table 26 1 Specifications of the ROM changed and Note added Figure 26 1 Block Diagram of ROM changed Table 26 3 Registers Related to ROM changed 26 2 2 Flash Access Status Register FASTAT bit ROMAE Bit description Note added 26 2 6 Flash Status Register 1 FSTATR1 Bit allocation Value after a ...

Page 997: ...ly changed 27 8 Boot Mode added 905 to 925 909 Section 28 Electrical Characteristics Vref VREFH AVSS VREFL changed Table 28 5 Clock Timing tcyc tCH tCL changed 1 00 Mar 16 2010 31 32 35 to 40 46 50 1 Overview Figure 1 2 Block Diagram Ports F to H added Figure 1 3 Pin Assignment of the 176 pin LFBGA added Table 1 3 List of Pins and Pin Functions 176 Pin LFBGA added Table 1 5 Pin Functions Descripti...

Page 998: ...ption on PF PG and PH added Table 14 10 Treatment of Unused Pins added 14 6 3 Port Setting when A D Converter Input is Used added 757 757 22 I2 C Bus Interface RIIC 22 15 5 Notes when Communication is Restarted with the NACK Reception in Master Mode added 22 15 6 Notes on the RDRF Flag Set Timing Selection Bit RDRFS added 787 787 23 A D Converter 23 6 7 Ranges of Settings for Analog Power Supply a...

Page 999: ...ses address order changed Table 5 1 List of I O Registers Address Order ISELR253 register added Table 5 2 List of I O Registers Bit Order ISELR253 register added Table 5 2 List of I O Registers Bit Order Bit name in SSR register changed 170 175 183 196 8 Low Power Consumption Figure 8 1 Mode Transitions changed 8 2 2 Module Stop Control Register A MSTPCRA Description added 8 2 7 Deep Standby Inter...

Page 1000: ...Mode Normal Transfer Mode Block Size 3 Title and timing changed Figure 13 12 Example of DTC Operation Timing 3 Short Address Mode Chain Transfer changed Figure 13 13 Example of DTC Operation Timing 4 Full Address Mode Normal Transfer Mode Repeat Transfer Mode changed 13 4 8 Execution State of the DTC changed Table 13 10 Execution State of the DTC changed 437 to 443 14 I O Ports Table 14 8 Settings...

Page 1001: ... I2 C Bus Interface RIIC 22 2 5 I2 C Bus Mode Register 3 ICMR3 Description on the bit table changed 22 2 14 I2 C Bus Bit Rate High Level Register ICBRH changed 22 3 4 Master Receiver Operation 5 6 changed Figure 22 10 Example of Master Reception Flowchart 7 Bit Address Format changed Figure 22 13 Master Receive Operation Timing 3 when RDRFS 0 changed Figure 22 31 Automatic Low Hold Operation in Re...

Page 1002: ...ulation Instructions description changed 11 5 5 5 Restriction on Instruction Code description changed 359 360 13 Data Transfer Controller DTC Figure 13 11 Example of DTC Operation Timing 2 Short Address Mode Block Transfer Mode Block Size 3 title changed Figure 13 12 Example of DTC Operation Timing 3 Short Address Mode Chain Transfer and Figure 13 13 Example of DTC Operation Timing 4 Full Address ...

Page 1003: ... Flowchart 7 Bit Address Format changed Figure 22 14 Example of Slave Transmission Flowchart changed Figure 22 17 Example of Slave Reception Flowchart changed Figure 22 36 Start Condition Restart Condition Issue Timing ST and RS Bits changed 803 23 A D Converter 23 6 8 Point for Caution Regarding Board Design changed 832 852 890 905 to 906 26 ROM 26 2 8 Flash P E Mode Entry Register FENTRYR change...

Page 1004: ...RX610 Group User s Manual Hardware Publication Date Rev 0 11 Apr 15 2009 Rev 1 20 Feb 20 2013 Published by Renesas Electronics Corporation ...

Page 1005: ...205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9...

Page 1006: ...RX610 Group R01UH0032EJ0120 ...

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