Renesas RX600 Series, User Manual

Page: 342 / 1006

RX610 Group 13. Data Transfer Controller (DTC)
R01UH0032EJ0120 Rev.1.20 Page 342 of 1006
Feb 20, 2013
ERR Flag (Transfer Stop Flag)
The ERR flag indicates that a DTC transfer stop request is present due to a bus error or nonmaskable interrupt.
When the DTC accepts a transfer stop request, it stops data transfer.
[Setting condition]
• When a nonmaskable interrupt is generated, or when a bus error is generated
[Clearing condition]
• When the corresponding source flag is cleared on completion of processing for the nonmaskable interrupt, or when the
bus error source is cleared on completion of processing for the bus error interrupt
RCHNE Bit (Chain Transfer Enable after DTC Repeat Transfer)
The RCHNE bit enables or disables chain transfer when data transfer of the specified count ends (transfer counter = 0) in
repeat transfer mode.
When the transfer counter CRAL becomes 00h in repeat transfer mode, chain transfer is not performed because the
CRAH value is written to CRAL. Writing 1 to the RCHNE bit enables chain transfer when the transfer counter is
rewritten.
RRS Bit (DTC Transfer Data Read Skip Enable)
The DTC vector number is always compared with the vector number in the previous startup process.
When these vector numbers match and the RRS bit is set to 1, DTC data transfer is performed without reading the
transferred data. However, when the previous transfer was chain transfer, the transferred data is always read regardless of
the value of RRS bit.
Furthermore, when the transfer counter (CRA register) became 0 during the previous normal transfer and when the
transfer counter (CRB register) became 0 during the previous block transfer, the transferred data is always read regardless
of the value of RRS bit.
13.2.8 DTC Vector Base Register (DTCVBR)
Address: 0008 7404h
b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b20 b31 b24 b23 b19 b18 b17 b16 b30 b29 b28 b27 b26 b25 b22 b21
Value after reset:
Value after reset:
DTCVBR is used to set the base address for calculating the DTC vector table address.
The lower 12 bits (b11 to b0) are always 0 and cannot be modified.
The upper 4 bits (b31 to b28) are ignored, and the address of this register is extended by the value specified by b27.