Renesas RX600 Series, User Manual

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2.5.4.1 Data Arrangement in Registers ........................................................................................................... 73
2.5.4.2 Data Arrangement in Memory ............................................................................................................. 73
2.5.5 Notes on Arrangement of Instruction Code ............................................................................................. 73
2.6 Vector Table ...................................................................................................................................................... 74
2.6.1 Fixed Vector Table ................................................................................................................................... 74
2.6.2 Relocatable Vector Table ......................................................................................................................... 75
2.7 Operation of Instructions ................................................................................................................................... 76
2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions ............................ 76
2.8 Pipeline ............................................................................................................................................................. 77
2.8.1 Overview .................................................................................................................................................. 77
2.8.2 Instructions and Pipeline Processing ........................................................................................................ 79
2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ................................... 79
2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing .............................. 81
2.8.2.3 Pipeline Basic Operation ..................................................................................................................... 84
2.8.3 Calculation of the Instruction Processing Time ....................................................................................... 86
2.8.4 Numbers of Cycles for Response to Interrupts ........................................................................................ 87
3. Operating Modes ........................................................................................................................................ 88
3.1 Operating Mode Types and Selection ............................................................................................................... 88
3.2 Register Descriptions ........................................................................................................................................ 89
3.2.1 Mode Monitor Register (MDMONR) ...................................................................................................... 89
3.2.2 Mode Status Register (MDSR) ................................................................................................................ 90
3.2.3 System Control Register 0 (SYSCR0) ..................................................................................................... 91
3.2.4 System Control Register 1 (SYSCR1) ..................................................................................................... 93
3.3 Details of Operating Modes .............................................................................................................................. 94
3.3.1 Single-Chip Mode .................................................................................................................................... 94
3.3.2 On-Chip ROM Enabled Extended Mode ................................................................................................. 94
3.3.3 On-Chip ROM Disabled Extended Mode ................................................................................................ 94
3.3.4 Boot Mode................................................................................................................................................ 94
3.3.5 User Boot Mode ....................................................................................................................................... 94
3.4 Transitions of Operating Modes ........................................................................................................................ 95
3.4.1 Operating Mode Transitions According to Mode Pin Setting .................................................................. 95
3.4.2 Operating Mode Transitions According to Register Setting .................................................................... 96
4. Address Space ............................................................................................................................................ 97
4.1 Address Space ................................................................................................................................................... 97
4.2 External Address Space ................................................................................................................................... 101
5. I/O Registers ............................................................................................................................................. 102
5.1 I/O Register Addresses (Address Order) ......................................................................................................... 104
5.2 I/O Register Bits .............................................................................................................................................. 125