RX610 Group
9. Exceptions
R01UH0032EJ0120 Rev.1.20
Page 206 of 1006
Feb 20, 2013
When an exception is accepted, hardware processing by the RX CPU is followed by vector access to acquire the address
of the branch destination. A vector address is allocated to each exception. The branch destination address of the handler
for the given exception is written to each vector address. The combination is referred to as a vector.
Hardware pre-processing by the RX CPU handles saving of the contents of the program counter (PC) and processor
status word (PSW). In the case of the fast interrupt, the contents are saved in the backup PC (BPC) and the backup PSW
(BPSW), respectively. In the case of other exceptions, the contents are preserved in the stack area.
General purpose registers and control registers other than the PC and PSW that are to be used within the exception
handling routine must be preserved on the stack by user program code at the start of the exception handling routine.
On completion of processing by most exception processing handlers, registers preserved under program control are
restored and the RTE instruction is executed to restore execution from the exception handling routine to the original
program. For return from the fast interrupt, the RTFI instruction is used instead. In the case of the non-maskable interrupt,
however, end the program or reset the system without returning to the original program.
Hardware post-processing by the RX CPU handles restoration of the pre-exception contents of the PC and PSW. In the
case of the fast interrupt, the contents of the BPC and BPSW are restored to the PC and PSW, respectively. In the case of
other exceptions, the contents are restored from the stack area to the PC and PSW.
Summary of Contents for RX600 Series
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