RX610 Group
20. Serial Communications Interface (SCI)
R01UH0032EJ0120 Rev.1.20
Page 670 of 1006
Feb 20, 2013
Initialization
Read data from RDR
Clear bits RIE and RE
in SCR to 0
Start data reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and PER = 0?
RXI interrupt
All data received?
Yes
Figure 20.29 Sample Serial Reception Flowchart
20.5.8
Clock Output Control
Clock output can be fixed using the CKE[1:0] bits in SCR when the GM bit in SMR is set to 1. Specifically, the
minimum width of a clock pulse can be specified.
Figure 20.30 shows an example of clock output stop timing when the CKE0 bit is controlled with GM = 1 and
CKE1 = 0.
Given pulse width
SCR.CKE0 bit
SCKn
Given pulse width
Figure 20.30 Clock Output Stop Timing
At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock
duty cycle.
Summary of Contents for RX600 Series
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