Renesas RX600 Series, User Manual

Page: 767 / 1006

RX610 Group 22. I
2
C Bus Interface (RIIC)
R01UH0032EJ0120 Rev.1.20 Page 767 of 1006
Feb 20, 2013
22.12 SMBus Operation
The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus
communication, set the SMBS bit in ICMR3 to 1 to select input level conforming to the SMBus for the SCLn pin/SDAn
pin function. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus standard, set the CKS[2:0] bits
in ICMR1, ICBRH, and ICBRL. In addition, determine the values of the DLCS bit in ICMR2 and the SDDL[2:0] bits in
ICMR2 to meet the data hold time specification of 300 ns or more. When the RIIC is used only as a slave device, the
transfer rate setting is not necessary, whereas the ICBRL needs to be set to a value longer than the data setup time (250
ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (SARL0, SARL1, and
SARL2), and set the corresponding FS bit (7-bit/10-bit address format select) in SARUy (y = 0 to 2) to 0 (7-bit address
format).
When transmitting the UDID (Unique Device Identifier), set the SALE bit in ICFER to 1 to enable the slave arbitration
lost detection function.
22.12.1 SMBus Timeout Measurement
(1)
Measuring timeout of slave device
The following period (timeout interval: T
LOW: SEXT
) must be measured for slave devices in SMBus communication.
• From start condition to stop condition
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
the TPU or TMR timer using a start condition detection interrupt (STI) and stop condition detection interrupt (SPI) of the
RIIC. The measured timeout period must be within the total clock low-level period [slave device] T
LOW: SEXT
: 25 ms
(max.) of the SMBus standard.
If the time measured with the TPU or TMR exceeds the clock low-level detection timeout T
TIMEOUT
: 25 ms (min.) of the
SMBus standard, the slave device must release the bus by writing 1 to the IICRST bit in ICCR1 to issue an internal reset
of the RIIC. When an internal reset is issued, the RIIC stops driving the bus for the SCLn pin and SDAn pin and make
the SCLn/SDAn pin outputs high impedance, which releases the bus.
(2)
Measuring timeout of master device
The following periods (timeout interval: T
LOW: MEXT
) must be measured for master devices in SMBus communication.
• From start condition to acknowledge bit
• Between acknowledge bits
• From acknowledge bit to stop condition
To measure timeout for master devices, measure these periods with the TPU or TMR timer using a start condition
detection interrupt (STI), stop condition detection interrupt (SPI), and transmit end interrupt (ICTEI) or receive data full
interrupt (ICRXI) of the RIIC. The measured timeout period must be within the total clock low-level extended period
[master device] T
LOW: MEXT
: 10 ms (max.) of the SMBus standard, and the total of all T
LOW: MEXT
from start condition to
stop condition must be within T
LOW: SEXT
: 25 ms (max.).
For the ACK receive timing (rising edge of the ninth SMBCLK clock cycle), monitor the TEND flag in ICSR2 in master
transmit mode (master transmitter) and the RDRF flag in ICSR2 in master receive mode (master receiver). For this
reason, perform bytewise transmit operation in master transmit mode, and hold the RDRFS bit in ICMR3 0 until the byte
just before reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 at the
rising edge of the ninth SMBCLK clock cycle.