Renesas RX600 Series, User Manual

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RX610 Group 2. CPU
R01UH0032EJ0120 Rev.1.20 Page 84 of 1006
Feb 20, 2013
2.8.2.3 Pipeline Basic Operation
In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due
to the processing and the branch execution.
The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the
unit of micro-operations.
The figures below show the pipeline processing of typical cases. Small letters in figures indicate micro-operations.
[Legend]
mop: Micro-operation, stall: Pipeline stall
(1)
Pipeline Flow with Stalls
IF D E E E WB
IF D stall E WB stall
IF
stall
E WB D
stall
(mop) div
(mop) add
(mop) add
Figure 2.20 When an Instruction which Requires Multiple Cycles is Executed in the E Stage
IF D E M
M WB
IF D E M WB stall
IF D WB E
stall
M
stall
stall
Other than no-wait
memory access
(mop) load
(mop) add
Figure 2.21 When an Instruction which Requires
more than One Cycle for its Operand Access is Executed
IF D E
Branch
instruction
Branch instruction is executed
IF D E WB
Branch penalty
Two cycles
(mop) jump
Figure 2.22 When a Branch Instruction is Executed (While the Condition is Satisfied for
Unconditional/Conditional Branch Instruction)