Renesas RX600 Series, User Manual

Page: 226 / 1006

RX610 Group 10. ICU
R01UH0032EJ0120 Rev.1.20 Page 226 of 1006
Feb 20, 2013
10.2.3 Interrupt Request Enable Register m (IERi) (i = 02h to 1Fh)
IEN2 IEN1
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 0 0 0 0 0
IEN7 IEN6 IEN5 IEN4 IEN3 IEN0
Addresses: 0008 7202h to 0008 721Fh
Bit Symbol Bit Name Description R/W
*
b0 IEN0 Interrupt Request Enable 0 0: Interrupt request is disabled
1: Interrupt request is enabled R/W
b1 IEN1 Interrupt Request Enable 1 R/W
b2 IEN2 Interrupt Request Enable 2 R/W
b3 IEN3 Interrupt Request Enable 3 R/W
b4 IEN4 Interrupt Request Enable 4 R/W
b5 IEN5 Interrupt Request Enable 5 R/W
b6 IEN6 Interrupt Request Enable 6 R/W
b7 IEN7 Interrupt Request Enable 7 R/W
Note:
*
Write 0 to the bit that corresponds to the interrupt source for reservation. Such a bit is read as 0.
The IERm register is used to enable or disable an interrupt request to the CPU and DMAC/DTC activation request.
IENj Bits (Interrupt Request Enable) (j = 0 to 7)
There is an interrupt request enable bit for each interrupt source.
For the correspondence between interrupt sources and interrupt request enable bits, see table 10.4, Interrupt Vector Table.
When an IENj bit is 1, the corresponding interrupt request is enabled. When an IENj bit is 0, the corresponding interrupt
request is disabled.
The IRi.IR flag is not affected by the IENj bit. Even if the IENj bit is 0, the IR flag changes under the conditions
described in section 10.2.1, Interrupt Request Register i (IRi) (i = interrupt vector number). The correspondence between
the interrupt sources and the IERm.IENj bits, refer to table 10.4, Interrupt Vector Table. For IERm.IENj bit setting
procedure for selection of the interrupt request destination, refer to section 10.4.3, Selecting Interrupt Request
Destinations.