RX610 Group
2. CPU
R01UH0032EJ0120 Rev.1.20
Page 72 of 1006
Feb 20, 2013
Table 2.12 8-Bit Write Operations when Big Endian has been Selected
Operation
Address of dest
Writing an 8-bit unit to
address 0
Writing an 8-bit unit to
address 1
Writing an 8-bit unit to
address 2
Writing an 8-bit unit to
address 3
Address 0
Transfer from LL
Address 1
Transfer from LL
Address 2
Transfer from LL
Address 3
Transfer from LL
2.5.2
Access to I/O Registers
The addresses of I/O registers are fixed, and this is regardless of whether the setting on the MDE pin is for little endian or
big endian. Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers,
refer to the descriptions of registers in the relevant sections.
2.5.3
Notes on Access to I/O Registers
Ensure that access to I/O registers is in accord with the following rules.
•
For I/O registers designated as having a bus width of eight bits, use instructions for an eight-bit bus width.
•
For I/O registers designated as having a bus width of 16 bits, use instructions for a 16-bit bus width.
•
For I/O registers designated as having a bus width of 32 bits, use instructions for a 32-bit bus width.
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...
