Renesas RX600 Series, User Manual

Page: 390 / 1006

RX610 Group 14. I/O Ports
R01UH0032EJ0120 Rev.1.20 Page 390 of 1006
Feb 20, 2013
14.2.13 Port Function Control Register 6 (PFCR6)
Value after reset:
Address: 0008 C106h
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
TPUMS5 TPUMS4 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B
0
Bit Symbol Bit Name Description R/W
b0 TPUMS0B Multifunction Select 0B
for TPU I/O Pins
0: Output compare and input capture are allocated to P32.
1: Input capture and output compare are allocated to P33 and P32,
respectively.
R/W
b1 TPUMS0A Multifunction Select 0A
for TPU I/O Pins
0: Output compare and input capture are allocated to P30.
1: Input capture and output compare are allocated to P31 and P30,
respectively.
R/W
b2 TPUMS1 Multifunction Select 1 for
TPU I/O Pins
0: Output compare and input capture are allocated to P34.
1: Input capture and output compare are allocated to P35 and P34,
respectively.
R/W
b3 TPUMS2 Multifunction Select 2 for
TPU I/O Pins
0: Output compare and input capture are allocated to P36.
1: Input capture and output compare are allocated to P37and P36,
respectively.
R/W
b4 TPUMS3B Multifunction Select 3B
for TPU I/O Pins
0: Output compare and input capture are allocated to P22.
1: Input capture and output compare are allocated to P23 and P22,
respectively.
R/W
b5 TPUMS3A Multifunction Select 3A
for TPU I/O Pins
0: Output compare and input capture are allocated to P21.
1: Input capture and output compare are allocated to P20 and P21,
respectively.
R/W
b6 TPUMS4 Multifunction Select 4 for
TPU I/O Pins
0: Output compare and input capture are allocated to P25.
1: Input capture and output compare are allocated to P24 and P25,
respectively.
R/W
b7 TPUMS5 Multifunction Select 5 for
TPU I/O Pins
0: Output compare and input capture are allocated to P26.
1: Input capture and output compare are allocated to P27 and P26,
respectively.
R/W
PFCR6 is used to select the multiplexed function for the TPU (unit 0) I/O pins.
Setting the TPUMS0A, TPUMS1, TPUMS2, TPUMS3A, PUTMS4, and TPUMS5 bits to 1 enables the input capture
inputs of TGRA and TGRB of the TPUn to be allocated to the same pin. Setting the TPUMS0B and TPUMS3B bits to 1
enables the input capture inputs of TGRC and TGRD of the TPUn to be allocated to the same pin.
By setting the timer mode register of the TPU (TPUn.TMDR), it is possible to set the input capture inputs of TRGA and
TRGB or TRGC and TRGD to the same pin.
Table 14.6 shows the correspondences between the PFCR6 and TPUn.TMDR settings and the input capture inputs and
external pins.
TPUMS0B Bit (Multifunction Select 0B for TPU I/O Pins)
This bit selects an input pin for TIOCC0.