RX610 Group
20. Serial Communications Interface (SCI)
R01UH0032EJ0120 Rev.1.20
Page 663 of 1006
Feb 20, 2013
20.5.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card
interface mode.
In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit
rate according to the settings of the BCP2 bit in SCMR and BCP[1:0] bits in SMR (the frequency is always 16 times the
bit rate in normal asynchronous mode).
For data reception, the falling edge of the start bit is sampled with the base clock to perform internal synchronization. For
data reception, the falling edge of the start bit is sampled with the base clock to perform internal synchronization.
Receive data is sampled on the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, and 256th rising edges of the base clock so that
it can be latched at the middle of each bit as shown in figure 20.24. The reception margin here is determined by the
following formula.
M = (0.5 - ) - (L - 0.5) F - (1+F)
1
2N
D - 0.5
N
×
100 [%]
[Legend]
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula
below.
M = {0.5 - 1/(2 x 372)}
×
100 (%) = 49.866%
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...
