Renesas RX600 Series, User Manual

Page: 230 / 1006

RX610 Group 10. ICU
R01UH0032EJ0120 Rev.1.20 Page 230 of 1006
Feb 20, 2013
10.2.7 IRQ Control Register n (IRQCRn) (n = 0 to 15)
— —
Addresses: 0008 C320h to 0008 C32Fh
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 0 0 0 0 0
— — — — IRQMD[1:0]
Bit Symbol Bit Name Description R/W
b1, b0

Reserved These bits are read as 0. The write value should
always be 0.
R/W
b3, b2 IRQMD[1:0] IRQ Detection Select
b3 b2
0 0: Low level
0 1: Falling edge
1 0: Rising edge
1 1: Rising and falling edges
R/W
b7 to b4

Reserved These bits are read as 0. The write value should
always be 0.
R/W
The IRQCRn register is used to set up the external interrupt IRQn pin (n = 0 to 15).
The contents of this register should be modified while the corresponding interrupt request enable bit is set to disable an
interrupt request (IERm.IENj bit is 0). After modification of the contents of this register, the IR flag should be cleared,
and then the interrupt request enable bit should be set to enable the interrupt request.
IRQMD[1:0] Bits (IRQ Detection Sense Select)
These bits select the detection method for external interrupt source IRQn, where n = 0 to 15.
For setting to detect the corresponding external interrupt source, see section 10.4.6, External Interrupts.