RX610 Group
15. 16-Bit Timer Pulse Unit (TPU)
R01UH0032EJ0120 Rev.1.20
Page 520 of 1006
Feb 20, 2013
15.9.3
Caution on Cycle Setting
When counter clearing by compare match is set, TPUm.TCNT is cleared in the final state in which it matches the
TPUm.TGRy value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter
frequency is given by the following formula:
f = PCLK
(N + 1)
f:
Counter frequency
PCLK: Operating frequency
N:
TGRy set value
15.9.4
Conflict between TPUm.TCNT Write and Clear Operations
If the counter clearing signal is generated in a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is
not performed. Figure 15.44 shows the timing in this case.
N
0000h
TCNT
PCLK
Counter clear signal
TCNT write by CPU
Figure 15.44 Conflict between TPUm.TCNT Write and Clear Operations
15.9.5
Conflict between TPUm.TCNT Write and Increment Operations
If incrementing occurs in a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure
15.45 shows the timing in this case.
TCNT
PCLK
TCNT input clock
TCNT write by CPU
M
X
TCNT write data
Figure 15.45 Conflict between TPUm.TCNT Write and Increment Operations
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...
