RX610 Group
22. I
2
C Bus Interface (RIIC)
R01UH0032EJ0120 Rev.1.20
Page 763 of 1006
Feb 20, 2013
22.11 Bus Hanging
If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I
2
C bus
might hang with a fixed level on the SCLn line and/or SDAn line.
As measures against the bus hanging, the RIIC has a timeout detection function to detect hanging by monitoring the
SCLn line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals
being out of synchronization, and the RIIC/internal reset function.
By checking the SCLO, SDAO, SCLI, and SDAI bits in ICCR1, it is possible to see whether the RIIC or its partner in
communications is placing the low level on the SCLn or SDAn lines.
22.11.1 Timeout Detection Function
The RIIC has the timeout detection function to detect an abnormality that the SCLn line is held for a certain period of
time. In the bus busy state, the RIIC can detect an abnormal bus state by monitoring that the SCLn line is held low or
high for a predetermined time.
The timeout detection function monitors the SCLn line state and counts the low-level period or high-level period using
the internal counter. The timeout detection function resets the internal counter each time the SCLn line changes (rising or
falling), but continues to count unless the SCLn line changes. If the internal counter overflows due to no SCLn line
change, the RIIC can detect the timeout and report the bus abnormality.
This timeout detection function is enabled when the TMOE bit in ICFER is 1. It detects an abnormal bus state that the
SCLn line is held low or high when the bus is busy (BBSY flag = 1 in ICCR2) in master mode or when the BBSY flag is
1 and the RIIC's own slave address matches (ICSR1 is not 00h) in slave mode.
The internal counter of the timeout detection function works using the internal reference clock (IIC
φ
) set by the CKS[2:0]
bits in ICMR1 as a count source. It functions as a 16-bit counter when long mode is selected (TMOS bit = 0 in ICMR2)
or a 14-bit counter when short mode is selected (TMOS bit = 1).
The SCLn line level (low/high or both levels) during which this counter is activated can be selected by the setting of the
TMOH and TMOL bits in ICMR2. If both TMOL and TMOH bits are cleared to 0, the internal counter does not work.
Summary of Contents for RX600 Series
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