Renesas RX600 Series, User Manual

Page: 686 / 1006

RX610 Group 22. I
2
C Bus Interface (RIIC)
R01UH0032EJ0120 Rev.1.20 Page 686 of 1006
Feb 20, 2013
22. I
2
C Bus Interface (RIIC)
The RX610 Group has two I
2
C bus interfaces (RIIC modules).
The RIIC module conforms with and provides a subset of the NXP I
2
C bus (inter-IC bus) interface functions.
22.1 Overview
Table 22.1 lists the specifications of the RIIC, figure 22.1 shows a block diagram of the RIIC, and figure 22.2 shows an
example of I/O pin connections to external circuits (I
2
C bus configuration example). Table 22.2 shows the input/output
pins of the RIIC.
Table 22.1 RIIC Specifications
Item Specifications
Communications format
•
I
2
C bus format or SMBus format
•
Master mode or slave mode selectable
•
Automatic securing of the various set-up times, hold times, and bus-free times for the transfer rate
Transfer rate Up to 1M bps
SCL clock For master operation, the duty cycle of the SCL clock is selectable in the range from 4% to 96%.
Issuing and detecting
conditions
Start, restart, and stop conditions are automatically generated.
Start conditions (including restart conditions) and stop conditions are detectable.
Slave address
•
Up to three slave-address settings can be made.
•
Seven- and ten-bit address formats are supported (along with the use of both at once).
•
General call addresses, device ID addresses, and SMBus host addresses are detectable.
Acknowledgement
•
For transmission, the acknowledge bit is automatically loaded.
Transfer of the next data for transmission can be automatically suspended on detection of a
not-acknowledge bit.
•
For reception, the acknowledge bit is automatically transmitted.
If a wait between the eighth and ninth clock cycles has been selected, software control of the value in
the acknowledge field in response to the received value is possible (i.e. the return of ACK or NACK is
selectable).
Wait function
•
In reception, the following periods of waiting can be obtained by holding the clock signal (SCL) at the low
level:
waiting between the eighth and ninth clock cycles; and
waiting between the ninth clock cycle and the first clock cycle of the next transfer (WAIT function)
SDA output delay function Timing of the output of transmitted data, including the acknowledge bit, can be delayed.
Arbitration
•
For multi-master operation
Operation to synchronize the SCL (clock) signal in cases of conflict with the SCL signal from another
master is possible.
When issuing the start condition would create conflict on the bus, loss of arbitration is detected by
testing for non-matching between the internal signal for the SDA line and the level on the SDA line.
In master operation, loss of arbitration is detected by testing for non-matching between the signal on the
SDA line and the internal signal for the SDA line.
•
Loss of arbitration due to detection of the start condition while the bus is busy is detectable (to prevent
the issuing of double start conditions).
•
Loss of arbitration in transfer of a not-acknowledge bit due to the internal signal for the SDA line and the
level on the SDA line not matching is detectable.
•
Loss of arbitration due to non-matching of internal and line levels for data is detectable in slave
transmission.