RX610 Group
18. Compare Match Timer (CMT)
R01UH0032EJ0120 Rev.1.20
Page 593 of 1006
Feb 20, 2013
18.3
Operation
18.3.1
Periodic Count Operation
When an internal clock is selected by bits CKS[1:0] in CMCR and the STRj (j = 0 to 3) bit in CMSTRy (y = 0 or 1) is set
to 1, CMCNT starts counting up using the selected clock.
When the value in CMCNT and the value in CMCOR match, CMCNT is cleared to 0000h. At the same time, a compare
match interrupt (CMIm) (m = 0 to 3) is generated. CMCNT then starts counting up again from 0000h. Figure 18.2 shows
the operation of the CMCNT counter.
Time
Counter cleared by compare match with CMCOR
CMCNT value
CMCOR
0000h
Figure 18.2 CMCNT Counter Operation
18.3.2
CMCNT Count Timing
One of four internal clocks (PCLK/8, PCLK/32, PCLK/128, and PCLK/512) obtained by dividing the peripheral clock
(PCLK) can be selected with the CKS[1:0] bits in CMCSR. Figure 18.3 shows the timing of CMCNT.
PCLK
Internal clock
CMCNT
N
N+1
N-1
Figure 18.3 CMCNT Count Timing
Summary of Contents for RX600 Series
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