RX610 Group
15. 16-Bit Timer Pulse Unit (TPU)
R01UH0032EJ0120 Rev.1.20
Page 523 of 1006
Feb 20, 2013
15.9.10
Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the write
to the buffer register is not performed. Figure 15.50 shows the timing in this case.
TCNT
TGRy
PCLK
Input capture signal
Buffer register
M
N
N
M
Buffer register write by CPU
Figure 15.50 Conflict between Buffer Register Write and Input Capture
15.9.11
Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, TPUm.TCNT counter is cleared with the generation of
the compare match interrupt and an overflow interrupt is generated.
Figure 15.51 shows the operation timing when a TPUm.TGRy compare match is specified as the clearing source and
FFFFh is set in TGRy.
FFFFh
TCNT input clock
Counter clear signal
TCNT
Overflow interrupt flag
(IR flag in IRi of ICU)
(i = interrupt vector number)
*
PCLK
Compare match interrupt flag
(IR flag in IRi of ICU)
(i = interrupt vector number)
*
0000h
Note:
*
For the corresponding interrupt vector number, see section 10, Interrupt Control Unit (ICU).
Figure 15.51 Conflict between Overflow and Counter Clearing
Summary of Contents for RX600 Series
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