RX610 Group
13. Data Transfer Controller (DTC)
R01UH0032EJ0120 Rev.1.20
Page 358 of 1006
Feb 20, 2013
13.4.6
Chain Transfer
Setting the CHNE bit in MRB to 1 allows multiple data transfers continuously on a single startup source. Chain transfer
can be set independently for registers SAR, DAR, CRA, and CRB that define data transfer, as well as for registers MRA
and MRB. Figure 13.9 shows chain transfer operation.
When the CHNE and CHNS bits in MRB are set to 1 and 0, respectively, no interrupt is issued to the CPU and no
interrupt source flag as the startup source is cleared, but chain transfer is performed instead based on the next transfer
information.
When the CHNE and CHNS bits in MRB are both set to 1, no interrupt is issued to the CPU and no interrupt source flag
as the startup source is cleared when the transfer counter value is 0, but chain transfer is performed instead based on the
next transfer information. When the transfer counter value is not 0, the interrupt is issued to the CPU and the interrupt
source flag as the startup source is cleared by setting the DISEL bit in MRB to 1.
In chain transfer, the interrupt is issued to the CPU or the interrupt source flag as the startup source is cleared upon
transfer completion caused by clearing the CHNE bit in MRB to 0.
For detailed chain transfer flow, refer to figure 13.4, Operation Flowchart of the DTC, and table 13.5, Chain Transfer
Conditions.
In repeat transfer mode, writing 1 to the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB enables chain
transfer after data transfer of transfer counter = 1.
Transfer data
CHNE bit = 1
Transfer data allocated in
user area
Data area
Transfer source data (1)
Transfer data
start address
Vector table
DTC vector
address
Transfer data
CHNE bit = 0
Transfer source data (1)
Transfer source data (2)
Transfer source data (2)
Figure 13.9 Chain Transfer Operation
Summary of Contents for RX600 Series
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