Renesas RX600 Series, User Manual

Page: 389 / 1006

RX610 Group 14. I/O Ports
R01UH0032EJ0120 Rev.1.20 Page 389 of 1006
Feb 20, 2013
14.2.12 Port Function Control Register 5 (PFCR5)
Value after reset:
Address: 0008 C105h
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
—
WR1BC1E
—
DHE TCLKS
— — —
0
Bit Symbol Bit Name Description R/W
b2 to b0

Reserved These bits are read as 0. The write value should be 0. R/W
b3 TCLKS TPU External Clock
Input Pin Select
0: P32, P33, P35, and P37 are designated as external clock
input pins.
1: P14 to P17 are designated as external clock input pins.
R/W
b4 DHE D15-to-D8 Enable 0: PE7 to PE0 are designated as I/O port pins.
1: PE7 to PE0 are designated as D15 to D8 pins (function as
part of the external data bus)
R/W
b5

Reserved This bit is read as 0. The write value should be 0. R/W
b6 WR1BC1E WR1#/BC1# Output
Enable
0: P51 is designated as an I/O port pin.
1: P51 is designated as the WR#1 or BC1# output pin.
R/W
b7

Reserved This bit is read as 0. The write value should be 0. R/W
PFCR5 is used to select external clock input pins for the TPU.
TCLKS Bit (TPU External Clock Input Pin Select)
This bit selects the external clock input pins for the TPU.
DHE Bit (D15-to-D8 Enable)
This bit enables or disables the input and output of data signals D15 to D8 on the PE7 to PE0 pins (valid in expansion
mode with on-chip ROM disabled or enabled).
Note: This setting must be in accord with the setting of the external bus width selection bits in the CSn control register
(CSnCNT.BSIZE[1:0]). If the value of the DHE bit is 0 but the width of the external bus is 16 bits, operation of the
port E pin functions will be disrupted. For details on the BSIZE[1:0] bits, see 11.3.1, CSn Control Register
(CSnCNT).
WR1BC1E Bit (WR1#/BC1# Output Enable)
This bit enables or disables WR1#/BC1# output (valid in expansion mode with on-chip ROM disabled or enabled).