Renesas RX600 Series, User Manual

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RX610 Group 12. DMA Controller (DMAC)
R01UH0032EJ0120 Rev.1.20 Page 316 of 1006
Feb 20, 2013
12.2.9 DMA Current Transfer Byte Count Register (DMCBC)
Addresses: DMAC0.DMCBC 0008 2008h, DMAC1.DMCBC 0008 2018h
DMAC2.DMCBC 0008 2028h, DMAC3.DMCBC 0008 2038h
— — — —
b20 b31 b24 b23 b19 b18 b17 b16 b30 b29 b28 b27 b26 b25 b22 b21
b4 b15 b8 b7 b3 b2 b1 b0 b14 b13 b12 b11 b10 b9 b6 b5
Value after reset: x 0 0 0 0 0 0 x x x x x x x x x
Value after reset: x x x x x x x x x x x x x x x x
Note: x: Undefined
— —
Bit Description Setting Range R/W
b25 to b0 Number of DMA transfer bytes 0000000h to 3FFFFFFh R/W
b31 to b26 Reserved These bits are always read as 0. The write value should
always be 0.
R/W
DMCBC is used to set the number of DMA transfer bytes.
Do not set the DMCBC register of DMACm during data transfer, but set it while the DMAC is not active or DMA
transfer is disabled.
Access the DMCBC register of DMACm with 32 bits.
Write a multiple of 2 (for 16-bit data size) or a multiple of 4 (for 32-bit data size) to this register. Writing 0000000h to
this register makes the transfer byte count 64 Mbytes.
The value written to this register is transferred to the work register in the DMAC core at the beginning of DMA transfer.
The work register value decreases by the transfer byte count (1 for 8-bit data size, 2 for 16-bit data size, or 4 for 32-bit
data size) each time a single data block is transferred. When the work register value decreases to 0000000h, the DMA
transfer ends. The DMCBC register of DMACm is reloaded with the value from the working register on completion of a
single-operand transfer or of DMA transfer. However, when the BRLOD bit in DMCRA of DMACm is set to 1 (the
transfer byte count reload function is used), the value of the DMRBC register of DMACm is reloaded at the end of DMA
transfer.