17.
8-Bit Timer (TMR) ..................................................................................................................................... 561
17.1
Overview ......................................................................................................................................................... 561
17.2
Register Descriptions ...................................................................................................................................... 565
17.2.1
Timer Counter (TCNT) .......................................................................................................................... 566
17.2.2
Time Constant Register A (TCORA) ..................................................................................................... 566
17.2.3
Time Constant Register B (TCORB) ..................................................................................................... 567
17.2.4
Timer Control Register (TCR) ............................................................................................................... 568
17.2.5
Timer Counter Control Register (TCCR) ............................................................................................... 569
17.2.6
Timer Control/Status Register (TCSR) .................................................................................................. 571
17.3
Operation ......................................................................................................................................................... 573
17.3.1
Pulse Output ........................................................................................................................................... 573
17.3.2
Reset Input ............................................................................................................................................. 574
17.4
Operation Timing ............................................................................................................................................ 575
17.4.1
TCNT Count Timing .............................................................................................................................. 575
17.4.2
Timing of Interrupt Flag Setting to 1 at Compare Match ....................................................................... 576
17.4.3
Timing of Timer Output at Compare Match .......................................................................................... 577
17.4.4
Timing of Counter Clear by Compare Match ........................................................................................ 577
17.4.5
Timing of the External Reset for TCNT ................................................................................................ 578
17.4.6
Timing of Overflow Interrupt Flag Setting to 1 ..................................................................................... 579
17.5
Operation with Cascaded Connection ............................................................................................................. 580
17.5.1
16-Bit Count Mode ................................................................................................................................ 580
17.5.2
Compare Match Count Mode ................................................................................................................. 580
17.6
Interrupt Sources ............................................................................................................................................. 581
17.6.1
Interrupt Sources and DTC Activation ................................................................................................... 581
17.6.2
A/D Converter Activation ...................................................................................................................... 581
17.7
Usage Notes .................................................................................................................................................... 582
17.7.1
Module Stop State Setting ...................................................................................................................... 582
17.7.2
Notes on Setting Cycle ........................................................................................................................... 582
17.7.3
Conflict between TCNT Write and Counter Clear ................................................................................. 582
17.7.4
Conflict between TCNT Write and Increment ....................................................................................... 583
17.7.5
Conflict between TCORA or TCORB Write and Compare Match ........................................................ 584
17.7.6
Conflict between Compare Matches A and B ........................................................................................ 584
17.7.7
Switching of Internal Clocks and TCNT Operation ............................................................................... 585
17.7.8
Clock Source Setting with Cascaded Connection .................................................................................. 586
18.
Compare Match Timer (CMT) ................................................................................................................... 587
18.1
Overview ......................................................................................................................................................... 587
18.2
Register Descriptions ...................................................................................................................................... 588
18.2.1
Compare Match Timer Start Register 0 (CMSTR0) .............................................................................. 589
18.2.2
Compare Match Timer Start Register 1 (CMSTR1) .............................................................................. 590
Summary of Contents for RX600 Series
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