RX610 Group
11. Buses
R01UH0032EJ0120 Rev.1.20
Page 285 of 1006
Feb 20, 2013
(7) Tr1 to Trn (clock cycles of recovery)
Clock cycles of recovery can be inserted from the point where a bus cycle is completed. The number of clock cycles is
controlled by the setting of the read recovery (RRCV) or write recovery (WRCV) bits in the CSi recovery cycle setting
register (CSiREC). Both numbers of clock cycles of recovery are counted from the next cycle after the address hold time
and have values in the range from zero to 15 (clock cycles). For details on the clock cycles of recovery, see section 11.5.3,
Insertion of Recovery Cycles.
11.5.1.1
Normal Access
When the PRENB and PWENB bits in CSiMOD are set to 0 to disable page-reading and page-writing access,
respectively, all bus access will take the form of normal read and write operations.
Even when the PRENB and PWENB bits in CSiMOD are set to 1 to enable page-reading and page-writing access,
respectively, bus access other than page access will take the form of normal read and write operations.
Chip select/byte control
(CSn#/BC0#, BC1#)
Data read
(RD#)
Data bus
(D15 to D0)
External bus clock
(BCLK)
A
Normal read cycle wait (CSRWAIT)
Read-access CS extension cycle (CSROFF)
CS assert wait (CSON)
RD assert wait (RDON)
Address
(A23 to A0)
D
Tw1
Twn
Tend
Tn1
Tnm
Next bus access can be started
Tw2
Th
[Legend] n = 0 to 7
Figure 11.7 Bus Timing (Normal-Read Operation)
Summary of Contents for RX600 Series
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