Renesas RX600 Series, User Manual

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RX610 Group 19. Watchdog Timer (WDT)
R01UH0032EJ0120 Rev.1.20 Page 600 of 1006
Feb 20, 2013
19.2.2 Timer Control/Status Register (TCSR)
Address: 0008 8028h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: x 0 0 1 1 0 0 0
— TMS TME —
CKS[2:0]
—
[Legend] x: Undefined
Bit Symbol Bit Name Description R/W
b2 to b0 CKS[2:0] Clock Select b2 b0
0 0 0: PCLK/4 (cycle: 20.4
µ
s)
0 0 1: PCLK/64 (cycle: 326.4
µ
s)
0 1 0: PCLK/128 (cycle: 652.8
µ
s)
0 1 1: PCLK/512 (cycle: 2.6 ms)
1 0 0: PCLK/2048 (cycle: 10.4 ms)
1 0 1: PCLK/8192 (cycle: 41.8 ms)
1 1 0: PCLK/32768 (cycle: 167.1 ms)
1 1 1: PCLK/131072 (cycle: 668.5 ms)
Note: The overflow cycle for PCLK = 50 MHz is indicated in
parentheses.
R/W
b4, b3

Reserved These bits are always read as 1. The write value should
always be 1.
R/W
b5 TME Timer Enable 0: TCNT stops counting and is initialized to 00h.
1: TCNT starts counting.
R/W
b6 TMS Timer Mode Select 0: Interval timer mode
When TCNT overflows, an interval timer interrupt (WOVI)
is requested.
1: Watchdog timer mode
When TCNT overflows, WDTOVF# is output.
R/W
b7

Reserved This bit is always read as an undefined value. The write
value should always be 1.
R/W
TCSR selects the clock source to be input to TCNT, and the timer mode.
To read this register, use 8-bit access.
To write to this register, write data to WINA in 16 bits.
For details, see section 19.5.1, Notes on Register Access.
CKS[2:0] Bits (Clock Select)
These bits select the clock source to be input to TCNT.
TME Bit (Timer Enable)
Selects whether TCNT starts or stops counting. When this bit is set to 1, TCNT starts counting. When this bit is cleared
to 0, TCNT stops counting and is initialized to 00h.
TMS Bit (Timer Select)
Selects whether the WDT is used as a watchdog timer or interval timer.