Renesas RX600 Series, User Manual

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RX610 Group 15. 16-Bit Timer Pulse Unit (TPU)
R01UH0032EJ0120 Rev.1.20 Page 484 of 1006
Feb 20, 2013
15.2.9 Timer Synchronous Register (TSYRA, TSYRB)
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
0 0 0 0 0 0 0 0
— —
SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Addresses: TSYRA 0008 8101h, TSYRB 0008 8171h
Bit Symbol Bit Name Description R/W
b0 SYNC0 Timer Synchronization 0 0: TCNT operates independently
(TCNT presetting/clearing is unrelated to other channels)
1: TCNT performs synchronous operation
*
(TCNT synchronous presetting/synchronous clearing is
possible)
R/W
b1 SYNC1 Timer Synchronization 1 R/W
b2 SYNC2 Timer Synchronization 2 R/W
b3 SYNC3 Timer Synchronization 3 R/W
b4 SYNC4 Timer Synchronization 4 R/W
b5 SYNC5 Timer Synchronization 5 R/W
b7, b6

Reserved These bits are read as 0. The write value should always be 0. R/W
Note:
*
To set synchronous operation, the SYNCj bit (j = 0 to 5) for at least two channels must be set to 1. To set
synchronous clearing, the TCNT clearing source must also be set by the CCLR[2:0] bits in TCR in addition to
the SYNCj bit.
TSYRA selects independent operation or synchronous operation for the TCNT counters of TPU0 to TPU5.
TSYRB selects independent operation or synchronous operation for the TCNT counters of TPU6 to TPU11.
SYNCj Bits (Timer Synchronization) (j = 0 to 5)
These bits select whether the TCNT operation is independent of or synchronized with TCNT of other channels.
When synchronous operation is selected, synchronous presetting of multiple TCNT counters and synchronous clearing
through counter clearing on another channel are possible.