Renesas RX600 Series, User Manual

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RX610 Group 17. 8-Bit Timer (TMR)
R01UH0032EJ0120 Rev.1.20 Page 569 of 1006
Feb 20, 2013
17.2.5 Timer Counter Control Register (TCCR)
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 0 0 0 0 0
TMRIS
Addresses: TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh
TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh
CSS[1:0] CKS[2:0]
Bit Symbol Bit Name Description R/W
b2 to b0 CKS[2:0] Clock Select
*
See table 17.5. R/W
b4, b3 CSS[1:0] Clock Source Select See table 17.5. R/W
b6, b5

Reserved These bits are always read as 0. The write value should
always be 0.
R/W
b7 TMRIS Timer Reset Detection Condition Select 0: Cleared at rising edge of the external reset
1: Cleared when the external reset is high
R/W
Note
*
To use an external clock, set the Pn.DDR.Bi bit for the corresponding pin to "0" and the PnICR.Bi bit to "1". For details, see
section 14, I/O Ports.
TCCR selects an internal clock source for TCNT and the condition for detecting external reset.
CKS[2:0] Bits (Clock Select)
CSS[1:0] Bits (Clock Source Select)
The CKS[2:0] and CSS[1:0] bits select a clock. For details, see table 17.5.
TMRIS Bit (Timer Reset Detection Condition Select)
This bit is enabled when the TCR.CCLR[1:0] bits are 11b (cleared by external reset input) and selects the condition for
detecting external reset (level or edge).