RX610 Group
20. Serial Communications Interface (SCI)
R01UH0032EJ0120 Rev.1.20
Page 643 of 1006
Feb 20, 2013
20.3.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Since receive data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each
bit, as shown in figure 20.5. Thus the reception margin in asynchronous mode is determined by formula (1) below.
M = (0.5 - ) - (L - 0.5) F - (1+F)
1
2N
D - 0.5
N
×
100 [%] Formula (1)
...
[Legend]
M: Reception margin
N: Ratio of bit rate to clock (N = 16 when ABCS in SEMR = 0, N = 8 when ABCS in SEMR = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 - 1/(2
×
16)}
×
100 (%) = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Note: * This is an example when the ABCS bit in SEMR is 0. When the ABCS bit is 1, a frequency of 8 times the bit
rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock.
Receive data (RxDn)
Internal base clock
D0
D1
Synchronization
sampling timing
Data sampling
timing
Start bit
8 clock pulses
16 clock pulses
0
15
7
7
0
15
7
0
Figure 20.5 Receive Data Sampling Timing in Asynchronous Mode
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...
