RX610 Group
14. I/O Ports
R01UH0032EJ0120 Rev.1.20
Page 438 of 1006
Feb 20, 2013
14.4
Settings to Enable Output of the Signals
Table 14.8 lists the settings to enable output from the individual pins of each port.
Table 14.8 Settings to Enable Output of the Signals from Each Port
Port
Corresponding
Peripheral
Module
Signal Name
for Setting
Output
Output
Signal
Name
Register Setting
for Selection of
Signals
Setting for Each Internal Module
P0
0
SCI6
TxD6_OE
TxD6
SCR.TE = 1
1
2
TMR2
TMO2_OE
TMO2
TCSR.OSA[1:0] = 01/10/11 or TCSR.OSB[1:0] = 01/10/11
SCI6
SCK6_OE
SCK6
When SCMR.SMIF = 1:
SMR.GM = 0, SCR.CKE[1:0] = 01 or SMR.GM = 1
When SCMR.SMIF = 0:
SMR.CM = 0, SCR.CKE[1:0] = 01 or SMR.CM = 1,SCR.CKE[1] = 0
3
SCI4
SCK4_OE
SCK4
When SCMR.SMIF = 1:
SMR.GM = 0, SCR.CKE[1:0] = 01 or SMR.GM = 1
When SCMR.SMIF = 0:
SMR.CM = 0, SCR.CKE[1:0] = 01 or SMR.CM = 1, SCR.CKE[1] = 0
4
SCI4
TxD4_OE
TxD4
SCR.TE = 1
5
TMR3
TMO3_OE
TMO3
TCSR.OSA[1:0] = 01/10/11 or TCSR.OSB[1:0] = 01/10/11
P1
0
1
SCI2
SCK2_OE
SCK2
When SCMR.SMIF = 1:
SMR.GM = 0, SCR.CKE[1:0] = 01 or SMR.GM = 1
When SCMR.SMIF = 0:
SMR.CM = 0, SCR.CKE[1:0] = 01 or SMR.CM = 1, SCR.CKE[1] = 0
2
3
SCI2
TxD2_OE
TxD2
SCR.TE = 1
4
RIIC1
SDA1_OE
SDA1
ICCR1.ICE = 1
5
SCI3
SCK3_OE
SCK3
When SCMR.SMIF = 1:
SMR.GM = 0, SCR.CKE[1:0] = 01 or SMR.GM = 1
When SCMR.SMIF = 0:
SMR.CM = 0, SCR.CKE[1:0] = 01 or SMR.CM = 1, SCR.CKE[1] = 0
RIIC1
SCL1_OE
SCL1
ICCR1.ICE = 1
6
RIIC0
SDA0_OE
SDA0
ICCR1.ICE = 1
7
SCI3
TxD3_OE
TxD3
SCR.TE = 1
RIIC0
SCL0_OE
SCL0
ICCR1.ICE = 1
Summary of Contents for RX600 Series
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