Renesas RX600 Series, User Manual

Page: 699 / 1006

RX610 Group 22. I
2
C Bus Interface (RIIC)
R01UH0032EJ0120 Rev.1.20 Page 699 of 1006
Feb 20, 2013
22.2.3 I
2
C Bus Mode Register 1 (ICMR1)
Addresses: RIIC0.ICMR1 0008 8302h, RIIC1.ICMR1 0008 8322h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 1 0 0 0 0
BCWP
BC[2:0] CKS[2:0]
MTWP
Bit Symbol Bit Name Description R/W
b2 to b0 BC[2:0] Bit Counter
*
b2 b1 b0
0 0 0: 9 bits
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
R/W
*
b3 BCWP BC Write Protect
*
0: Enables a value to be written in the BC[2:0] bits
(This bit is always read as 1.)
R/W
*
b6 to b4 CKS[2:0] Internal Reference Clock Selection b6 b5 b4
0 0 0: PCLK/1 clock
0 0 1: PCLK/2 clock
0 1 0: PCLK/4 clock
0 1 1: PCLK/8 clock
1 0 0: PCLK/16 clock
1 0 1: PCLK/32 clock
1 1 0: PCLK/64 clock
1 1 1: PCLK/128 clock
R/W
b7 MTWP MST/TRS Write Protect 0: Disables writing to the MST and TRS bits in ICCR2
1: Enables writing to the MST and TRS bits in ICCR2
R/W
Note:
*
Set the BCWP bit to 0 to rewrite the BC[2:0] bits. The BC[2:0] bits must be rewritten by using the MOV instruction.
ICMR1 specifies the internal reference clock source within the RIIC, indicates the number of bits to be transferred, and
protects the MST and TRS bits in ICCR2 from being written.
BC[2:0] Bits (Bit Counter)
These bits function as a counter that indicates the number of bits remaining to be transferred at the detection of a rising
edge on the SCLn line. Although these bits are writable and readable, it is not necessary to access these bits under normal
conditions.
To write to these bits, specify the number of bits to be transferred plus one (data is transferred with an additional
acknowledge bit) between transferred frames when the SCLn line is at a low level.
The values of the BC[2:0] bits return to 000b at the end of a data transfer including the acknowledge bit or when a start
condition including a restart condition is detected.