RX610 Group
11. Buses
R01UH0032EJ0120 Rev.1.20
Page 258 of 1006
Feb 20, 2013
11.2.3
Internal Peripheral Buses
Connection of peripheral modules to the internal peripheral buses is as described in table 11.3.
Table 11.3 Connection of Peripheral Modules to the Internal Peripheral Buses
Type of Bus
Peripheral Modules
Internal peripheral bus 1
•
DMAC
•
Interrupt controller
Internal peripheral bus 2
•
Peripheral modules other than those connected to internal peripheral bus 1
11.2.4
External Bus
Table 11.4 lists the specifications of the external bus.
Table 11.4 Specifications of the External Bus
Item
Description
External address
space
•
An external address space is divided into eight areas (CS0 to CS7) for management.
•
Chip select signals can be output for each area.
•
An 8-bit bus space or a 16-bit bus space is selectable for each area.
•
An endian mode can be specified for each area.
Wait control function
•
Recovery cycles can be inserted.
Read recovery: Up to 15 cycles
Write recovery: Up to 15 cycles
•
Cycle wait function: Wait for up to 31 cycles (page access: up to 7 cycles)
•
Wait control can be used to set up the following.
Timing of assertion and negation for chip-select signals (CS0# to CS7#)
The timing of assertion of the read signal (RD#) and write signals (WR0#, WR1#, and WR#)
The timing with which data output starts and ends
•
Write access mode: Single write strobe mode/byte strobe mode
Write buffer function
•
When write data from the bus master has been written to the write buffer, write access by the
bus master is completed.
Frequency
•
The external bus operates in synchronization with the external bus clock (BCLK).
Summary of Contents for RX600 Series
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