Renesas RX600 Series, User Manual

Page: 277 / 1006

RX610 Group 11. Buses
R01UH0032EJ0120 Rev.1.20 Page 277 of 1006
Feb 20, 2013
11.3.6 Bus Error Source Clear Register (BERCLR)
—
Address: 0008 1300h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 0 0 0 0 0
— — — — — —
STSCLR
Bit Symbol Bit Name Description R/W
0 STSCLR Bus Error Source Clear 0: No effect
1: Clears the bus-error source signals
R/(W)
*
b7 to b1

Reserved These bits are always read as 0. The write value should
always be 0.
R/W
Note:
*
Only the writing of 1 is effective; i.e. writing 0 has no effect.
STSCLR Bit (Bus Error Source Clear)
Writing 1 to this bit clears the internal bus-error source signals. Clear the bus-error source signals being retained by the
bus from within the handling routine for bus-error interrupts.
Writing 0 to this bit has no effect. The value 0 is always read from this bit.
11.3.7 Bus Error Monitoring Enable Register (BEREN)
TOEN
Address: 0008 1304h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset: 0 0 0 0 0 0 0 0
— — — — — —
IGAEN
Bit Symbol Bit Name Description R/W
0 IGAEN Illegal Address Access
Detection Enable
0: Illegal address access detection is disabled.
1: Illegal address access detection is enabled.
R/W
1 TOEN Time-out Detection
Enable
* 1 * 2
0: Time-out detection is disabled.
1: Time-out detection is enabled.
R/W
b7 to b2

Reserved These bits are always read as 0. The write value should
always be 0.
R/W
Notes: 1. When detection is disabled (the TOEN bit is cleared to 0), bus access can cause the bus to freeze.
2. Do not set the TOEN bit to the value that disables detection while time-out errors are being detected.
IGAEN Bit (Illegal Address Access Detection Enable)
This bit enables or disables detection of access to illegal addresses.
TOEN Bit (Time-out Detection Enable)
This bit enables or disables detection of time-out for bus operations.