RX610 Group
6. Resets
R01UH0032EJ0120 Rev.1.20
Page 157 of 1006
Feb 20, 2013
6.2.2
Reset Control/Status Register (RSTCSR)
Address: 0008 802Bh
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
0
0
0
1
1
1
1
1
WOVF
RSTE
—
—
—
—
—
—
Bit
Symbol
Bit Name
Description
R/W
b4 to b0
Reserved
These bits are always read as 1. The write value should
always be 1.
R/W
b5
Reserved
This bit is always read as 0. The write value should always
be 0.
R/W
b6
RSTE
Reset Enable
0: The LSI is not reset internally when TCNT overflows in
watchdog timer mode. (TCNT and TCSR of the WDT are
reset.)
1: The LSI is internally reset when TCNT overflows in
watchdog timer mode.
R/W
b7
WOVF
Watchdog Timer Overflow
Flag
0: TCNT has not overflowed in watchdog timer mode.
1: TCNT has overflowed in watchdog timer mode.
R/(W)
*
Note:
*
Only 0 can be written to this bit.
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset
signal.
RSTCSR is initialized to 1Fh by a reset signal from the RES# pin or a deep software standby reset, but not by the WDT
internal reset signal caused by a WDT overflow.
To read this register, use 8-bit access.
To write to this register, write data in WINB in 16 bits.
For details, see section 19.5.1, Notes on Register Access.
RSTE Bit (Reset Enable)
Selects whether or not this LSI is internally reset when TCNT overflows in watchdog timer mode.
WOVF Flag (Watchdog Timer Overflow)
Indicates that TCNT overflows in watchdog timer mode. This bit cannot be set to 1 in interval timer mode.
[Setting condition]
•
When TCNT overflows (changed form FFh to 00h) in watchdog timer mode
[Clearing condition]
•
Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...