Renesas RX600 Series, User Manual

Page: 12 / 1006

10.4.2.1 Interrupt Status Flag in Edge Detection ............................................................................................ 243
10.4.2.2 Interrupt Status Flag in Level Detection ............................................................................................ 244
10.4.3 Selecting Interrupt Request Destinations ............................................................................................... 246
10.4.4 Determining Priority .............................................................................................................................. 248
10.4.5 Fast Interrupt .......................................................................................................................................... 248
10.4.6 External Interrupts .................................................................................................................................. 249
10.5 Non-maskable Interrupt Operation .................................................................................................................. 250
10.6 Returning from Low Power Consumption Modes .......................................................................................... 251
10.6.1 Returning from Sleep Mode and All-Module Clock Stop Mode ........................................................... 251
10.6.2 Returning from Software Standby Mode ............................................................................................... 252
10.7 Usage Notes .................................................................................................................................................... 253
10.7.1 Notes when writing to the Register of the Interrupt Control Unit .......................................................... 253
10.7.2 Notes on the WAIT Instruction when the NMI Pin Interrupt is Used .................................................... 253
10.7.3 Notes on Transferring DMAC/DTC Using Communication Function (SCI, RIIC) ............................... 253
11. Buses ........................................................................................................................................................ 256
11.1 Overview ......................................................................................................................................................... 256
11.2 Description of Buses ....................................................................................................................................... 257
11.2.1 CPU Buses ............................................................................................................................................. 257
11.2.2 Internal Main Buses ............................................................................................................................... 257
11.2.3 Internal Peripheral Buses ....................................................................................................................... 258
11.2.4 External Bus ........................................................................................................................................... 258
11.2.5 Parallel Operation .................................................................................................................................. 260
11.3 Register Descriptions ...................................................................................................................................... 261
11.3.1 CSi Control Register (CSiCNT) (i = 0 to 7) ........................................................................................... 263
11.3.2 CSi Recovery Cycle Register (CSiREC) (i = 0 to 7).............................................................................. 265
11.3.3 CSi Mode Register (CSiMOD) (i = 0 to 7) ............................................................................................ 267
11.3.4 CSi Wait Control Register 1 (CSiWCNT1) (i = 0 to 7) ......................................................................... 269
11.3.5 CSi Wait Control Register 2 (CSiWCNT2) (i = 0 to 7) ......................................................................... 273
11.3.6 Bus Error Source Clear Register (BERCLR) ......................................................................................... 277
11.3.7 Bus Error Monitoring Enable Register (BEREN) .................................................................................. 277
11.3.8 Bus Error Interrupt Enable Register (BERIE) ........................................................................................ 278
11.4 Endian and Data Alignment ............................................................................................................................ 279
11.4.1 16-Bit Bus Space .................................................................................................................................... 279
11.4.2 8-Bit Bus Space ...................................................................................................................................... 280
11.5 Operation ......................................................................................................................................................... 283
11.5.1 Timing of External Bus Access .............................................................................................................. 283
11.5.1.1 Normal Access .................................................................................................................................. 285
11.5.1.2 Page Access ....................................................................................................................................... 290
11.5.2 External Wait Function .......................................................................................................................... 293
11.5.2.1 Normal Access .................................................................................................................................. 293