RX610 Group
27. Data Flash (Flash Memory for Data Storage)
R01UH0032EJ0120 Rev.1.20
Page 926 of 1006
Feb 20, 2013
27.6.3
Connections between FCU Modes and Commands
The sets of FCU commands that can be accepted in each of the FCU modes are fixed. Furthermore, which commands are
acceptable in a given FCU mode varies according to the state of the FCU.
Issuing of an FCU command must follow checking of the FCU's state after transitions of the FCU mode.
Commands that are acceptable in the various FCU modes and states are listed in table 27.7. Issuing a command that is not
currently acceptable leads to the FCU being placed in the command-locked state (see section 27.7.2, Error Protection).
Issuing of an FCU command must follow checking of the values of the FRDY, ILGLERR, ERSERR, and PRGERR bits
in FSTATR0 and of the FCUERR bit in FSTATR1 after transitions of the FCU mode. Furthermore, the CMDLK bit in
FASTAT can be checked to see if an error has occurred. The value of the CMDLK bit in FASTAT is the logical OR of
the ILGLERR, ERSERR, and PRGERR bits in FSTATR0 and the FCUERR bit in FSTATR1.
Table 27.7 Acceptable Commands and the State and Mode (Data Flash P/E Mode) of the FCU
P/E Normal Mode
Status read mode
Lock-bit read mode
P
rog
ra
m
m
ing s
us
p
en
de
d
E
ras
u
re s
us
pe
nde
d
O
the
r s
tat
e
P
ro
g
ra
mmi
n
g
o
r e
ra
s
u
re
P
roc
e
s
s
in
g t
o
s
us
pe
nd
pr
o
gr
am
m
in
g o
r e
ras
ur
e
B
lank
c
hec
k
ing
P
rog
ra
m
m
ing s
us
p
en
de
d
E
ras
u
re s
us
pe
nde
d
C
om
m
a
nd
-l
oc
k
ed s
tat
e
O
the
r s
tat
e
P
rog
ra
m
m
ing s
us
p
en
de
d
E
ras
u
re s
us
pe
nde
d
O
the
r s
tat
e
FSTATR0.FRDY bit
1
1
1
0
0
0
1
1
0/1
1
1
1
1
FSTATR0.SUSRDY bit
0
0
0
1
0
0
0
0
0
0
0
0
0
FSTATR0.ERSSPD bit
0
1
0
0
0/1
0
0
1
0
0
0
1
0
FSTATR0.PRGSPD bit
1
0
0
0
0/1
0
1
0
0
0
1
0
0
FASTAT.CMDLK bit
0
0
0
0
0
0
0
0
1
0
0
0
0
Normal mode transition
A
A
A
X
X
X
A
A
X
A
A
A
A
Status read transition
A
A
A
X
X
X
A
A
X
A
A
A
A
Lock-bit read transition
(lock bit read 1)
A
A
A
X
X
X
A
A
X
A
A
A
A
Peripheral clock notification
X
X
A
X
X
X
X
X
X
A
X
X
A
Programming
X
*
A
X
X
X
X
*
X
A
X
*
A
Block erasure
X
X
A
X
X
X
X
X
X
A
X
X
A
P/E suspension
X
X
X
A
X
X
X
X
X
X
X
X
X
P/E resumption
A
A
X
X
X
X
A
A
X
X
A
A
X
Status register clearing
A
A
A
X
X
X
A
A
A
A
A
A
A
Blank checking
A
A
A
X
X
X
A
A
X
A
A
A
A
[Legend]
A: Acceptable
*
: Only programming is acceptable for blocks other than the block where erasure was suspended
X: Not acceptable
Summary of Contents for RX600 Series
Page 1006: ...RX610 Group R01UH0032EJ0120 ...
